const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 1, /* 30 bit numerator of fractional loop divider */
.denominator = 60000, /* 30 bit denominator of fractional loop divider */
.src=0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
.ss_step = 0x6,
.ss_enable = 1,
.ss_stop = 0x240 /* 6MHz spread spectrum setting */
};
step, enable and stop are the only things I can find that need changing per the manual. I see the denominator is also taken into account when doing the calculations but that value makes sense to me. What else am I missing? The registers contain the values I would expect when I inspected them over JTAG.
