Problem with slow/missing ADC conversions in iMXRT1062

[mark_callaghan]

I am looking for help with a problem with occasional slow/missing conversions from dual ADCs on the MIMXRT1062.

We are developing a product and aiming to use MIMXRT1062 to collect 2 channel ADC conversions at 100kHz sample rate, ideally with simultaneous sampling (for phase correlation) using ADC1 and ADC2. I am developing code using MIMXRT1060-EVK.

I set up a PIT timer to deliver triggers at 100kHz to ADC_ETC TRIG0 and TRIG4, to trigger ADC1 and ADC2, on ADC1_HC1 and ADC2_HC1. The ADCs are configured with 37.5MHz clock (ADIV=10b => /4). I have two channels of DMA set up, triggered through DMAMUX by ADC1 DMA Req and ADC2 DMA Req. The setup of each DMA channel is the same, with a minor loop of 1 transfer, 2 bytes, from the respective ADC result register ADC1_R0 and ADC2_R0ADC1_R1 and ADC2_R1, and a major loop of 1000 transfers. For each channel, at the completion of the major loop, an interrupt routine counts the major loops and also with a flag enables setup of another EDMA SG transfer in the main code.

I cannot use the ADC_ETC DMA functions because there is only one ADC_ETC DMA request, and I need to transfer both ADC results, from different source addresses.

The system mainly works, but there are occasions (1 in ~2000 samples) when ADC1 or ADC2 stop conversions, for 42 samples ~420usec.

I have brought various signals out to IO pins using the XBAR. I count PIT pulses and ADC1 and ADC2 COCO pulses with the QTMR. The DMA interrupt at completion of the major loops checks the QTMR counts of PIT pulses and ADC_ETC COCO0 and ADC_ETC COCO4. I expect perhaps a difference of 1 or two counts between PIT and COCO due to timing races between the code and QTMR increments. But sometimes the PIT count is at ~1042 and the COCO count at 1000. i.e. ~42 samples. When the difference is greater than 10, I assert a GPIO output pin to trigger the oscilloscope.

When the sequence is running properly, using the scope I see the PIT timer pulse, and ~1.4 usec (ADC conversion time) later the COCO pulses from each ADC channel.

When the unequal PIT/COCO count check in the interrupt routine triggers, I see a pause in the COCO pulses for one channel on the scope. i.e. the PIT pulses are regular, at 10usec interval. But on one channel, the COCO pulses stop for ~42usec. This corresponds to 42 samples at 10usec sample period. This occurs on ADC1 or ADC2. It is not near the beginning or end of the DMA major loop.

When the pause in conversions occurs, ADC_ETC Error IRQ shows TRIG0_ERR or TRIG4_ERR in "ETC DONE_2 and DONE_ERR IRQ State" Register.

From the data sheet pg 3451:
Error interrupt occurs when there is an external trigger ignored by ADC_ETC due to the previous trigger not finished yet.

What could be causing the ADC conversion to take longer than the normal 1.4usec, or the ADC_ETC to not see the ADC COCO? Adding a scope trigger to the ADC_ETC Error IRQ shows that ADC_ETC COCO0 or COCO4 pulses stop, with a gap of ~420usec to the next COCO. See the scope trace. Ch1=PIT, Ch2 = ADC_ETC COCO0, Ch3 = ADC_ETC COCO4 (Ch4 is my scope trigger from ADC_ETC ERR IRQ)

ADC_ETC CTRL is 0x11. (TSC_BYPASS is 0)
TRIG0_CHAIN_1_0 reg is 0x20 (ADC1 hwts trig1, input channel 0)
other TRIG0 chain regs are zero
TRIG2, 3, chain regs are zero
TRIG4_CHAIN_1_0 reg is 0x2f (ADC2 hwts trig1, input channel 15)
TRIG5,6,7 chain regs are zero

I have tried this on two MIMXRT1060-EVK boards, one with MIMXRT1062-DVL6A, the other with MIMXRT1062-DVL6B.

I am using MCUXPRESSO IDE 11.7, and SDK 2.13.0 (although some code may be based on earlier SDKs)

I have spent a significant amount of time attempting to debug this issue. Has anyone else seen anything similar? Can I get some help from NXP support?

Cheers,

Mark

[_Leo_]

Thank you so much for your interest in our products and for using our community.

I noticed that you have another similar case, so I will follow up on this last one that I mention.

Have a nice day!

[mark_callaghan]

It's all very quiet. Should I open a ticket?