MIMXRT1024xxxxx_flexspi_nor.ld memory map questions

[davenadler]

Corrections and clarifications...

I'm using this NXP-provided LD file in a sample application and have a few questions...
NXP MIMXRT1024xxxxx_flexspi_nor.ld on github 

1. The 1024 has 256kb of RAM, but the LD file only shows 196kb in 2 areas (64kb and 128kb):

  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00010000
  m_data2               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00020000

Is the missing RAM in m_qacode? Is the following correct?

MEMORY
{
  /* ==== Internal Flash ==== */
  m_flash_config  (RX)  : ORIGIN = 0x60000000, LENGTH = 0x00001000
  m_ivt           (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000
  m_interrupts    (RX)  : ORIGIN = 0x60002000, LENGTH = 0x00000400
  m_text          (RX)  : ORIGIN = 0x60002400, LENGTH = 0x003FDC00
  /*
  ** ==== Internal SRAM ====
  ** iMX1024 has 256kB of internal 'FlexRAM' SRAM, which can be allocated across the M7's
  ** 3 memory interfaces (note each interface starts at a fixed address):
  **   I-TCM fast access for instructions; ie running code from RAM rather than slow flash
  **   D-TCM fast access for data
  **   OCM (On-Chip RAM) for access by 64-bit system AXI bus; faster for DMA but slower for MCU core
  */
  m_qacode        (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* assume  64kB for I-TCM at fixed address 0x00000000 */
  m_data          (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* assume  64kB for D-TCM at fixed address 0x20000000 */
  m_data2         (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00020000 /* assume 128kB for   OCM at fixed address 0x20200000 */
}

2. Only m_data (not m_data2) is used in this LD. This limits available RAM to 64kb. Why?

3. Is there any reason LD could not use m_data2 only, increasing available RAM to 128kb?

4. How do I find out how the memory is actually configured (ie on the EVK)?
Is there example code to read the fuses, cache control, etc. and report how the flex-RAM is configured?

5. At the end of the LD, there seem to be some problems with stack:
  a) Stack is placed twice, in two different locations: once after heap, and then at top of the memory section.
  b) comment says stack is initialized, but it is only allocated here, not initialized, right?

6. Is there an example LD which uses multiple memory sections, with matching RTL support?

Thanks in advance for any assistance,
Best Regards, Dave

[Kan_Li]

Hi @davenadler ,

Please kindly have my comments as below:

1. The 1024 has 256kb of RAM, but the LD file only shows 196kb in 2 areas (64kb and 128kb):

  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00010000
  m_data2               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00020000

Is the missing RAM in m_qacode? Is the following correct?

MEMORY
{
  /* ==== Internal Flash ==== */
  m_flash_config  (RX)  : ORIGIN = 0x60000000, LENGTH = 0x00001000
  m_ivt           (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000
  m_interrupts    (RX)  : ORIGIN = 0x60002000, LENGTH = 0x00000400
  m_text          (RX)  : ORIGIN = 0x60002400, LENGTH = 0x003FDC00
  /*
  ** ==== Internal SRAM ====
  ** iMX1024 has 256kB of internal 'FlexRAM' SRAM, which can be allocated across the M7's
  ** 3 memory interfaces (note each interface starts at a fixed address):
  **   I-TCM fast access for instructions; ie running code from RAM rather than slow flash
  **   D-TCM fast access for data
  **   OCM (On-Chip RAM) for access by 64-bit system AXI bus; faster for DMA but slower for MCU core
  */
  m_qacode        (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* assume  64kB for I-TCM at fixed address 0x00000000 */
  m_data          (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* assume  64kB for D-TCM at fixed address 0x20000000 */
  m_data2         (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00020000 /* assume 128kB for   OCM at fixed address 0x20200000 */
}

- Yes, the missing RAM is just the m_qacode section defined for ITCM, where the RAM applications usually run, but as you are referring to the LD file for flexspi nor flash which is used for the case when the application run directly from the flash, so m_qacode section is not used. so the LD file is correct, but if you want the LD file for RAM application, please refer to https://github.com/nxp-mcuxpresso/mcux-sdk/blob/eeec309b116922403fbea0c137122a2d5e2624e0/devices/MIM... instead.

2. Only m_data (not m_data2) is used in this LD. This limits available RAM to 64kb. Why?

- This section is defined for DTCM, which is 64KB by default.

3. Is there any reason LD could not use m_data2 only, increasing available RAM to 128kb?

- No such limitation at all. You may use m_data2 instead, but the SDK usually m_data for application data, while m_data2 is used as NCACHE_REGION for the buffers used by modules such as USB.

4. How do I find out how the memory is actually configured (ie on the EVK)?
Is there example code to read the fuses, cache control, etc. and report how the flex-RAM is configured?

-Please kindly refer to https://www.nxp.com/docs/en/application-note/AN12077.pdf for details.

5. At the end of the LD, there seem to be some problems with stack:
  a) Stack is placed twice, in two different locations: once after heap, and then at top of the memory section.
  b) comment says stack is initialized, but it is only allocated here, not initialized, right?

- Yes, your understanding is correct. The stack is initialized with its top and bottom pointer, which would be referred by the application/IDE , but no touch in the contents for sure.

6. Is there an example LD which uses multiple memory sections, with matching RTL support?

- I am sorry, but I could not get your point here. Do you want the LD file has RTL support?  I think it is just used by the complier/IDE. for LD file which uses multiple memory sections, you may refer to https://github.com/nxp-mcuxpresso/mcux-sdk/blob/eeec309b116922403fbea0c137122a2d5e2624e0/devices/MIM... in which the application runs in the ITCM and data is stored in the SDRAM.

Hope that helps,

Have a great day,
Kan

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[davenadler]

1,2,3) OK, thanks.

4) I have read AN12077. Is there example code that reads the fuses, GPR14-17, MPU, and reports on memory configuration including caching?

5) Do you agree that the .stack section in LD is unused and incorrect, and that the comment before the actual stack placement is incorrect?

6) As other users have stated, we need good examples that show:
a) change default FlexRAM memory setup,
b) RTL correct initialization of RAM (bss, data) in DTCM and OCRAM,
c) RTL correct initialization of caching; setup in this LD looks incorrect:
__NCACHE_REGION_START = ORIGIN(m_data2);
__NCACHE_REGION_SIZE = 0;
conflicts with later placement of non-cacheable data.

Thanks!

[Kan_Li]

Hi @davenadler ,

Please kindly have my comments as below:

4) I have read AN12077. Is there example code that reads the fuses, GPR14-17, MPU, and reports on memory configuration including caching?

- There is no ready example for that purpose, but we have SDK demo code for OCOTP which can be used to read the fuses , and you may use it as a starting point.

5) Do you agree that the .stack section in LD is unused and incorrect, and that the comment before the actual stack placement is incorrect?

- No, I don't think so. The purpose of .stack section is used to change the length of m_data which can be used to define __StackTop and __StackLimit. 

6) As other users have stated, we need good examples that show:
a) change default FlexRAM memory setup, - The default flexRAM setup can only be changed by burning the fuses, not the LD file at all.
b) RTL correct initialization of RAM (bss, data) in DTCM and OCRAM,

- The SDK does this task in the start up code, so LD file here just provides the pointers to application code . Please kindly refer to the following for details.

c) RTL correct initialization of caching;setup in this LD looks incorrect:
__NCACHE_REGION_START = ORIGIN(m_data2);
__NCACHE_REGION_SIZE = 0;
conflicts with later placement of non-cacheable data.

-Actually those definitions are used by IAR instead. MCUXpresso looks for the definition from the later non-cacheable data placement.

Hope that makes sense,

Have a great day,
Kan

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- We are following threads for 7 weeks after the last post, later replies are ignored
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