Hi Dear Authorized,
I am trying to create a SRAM Application with SEMC. The slave (opponent side) of IMXRT is a FPGA. I am writing sequential data with attached code as you seen in my memory browser monitor.
The Memory Browser Monitor:
Transmitted by IMXRT1064: 0x0000_0000, 0x0000_0002, 0x0000_0004, 0x0000_0006 ....
The Data Acquired by FPGA:
Received by FPGA: 0xFFDF_0000 , 0xFFFF_0002, 0xFFDF_0004, 0xFFDF_0006 ....
I am curious about why the data is acquiring in corrupted order in FPGA Side. We are monitoring FPGA data in logic analyzer.
I just tried different things checked connection pins everything looks ok. I can't understand where the problem is.
Is there a possibility to corrupt data which caused by my code even if data seen correct in memory monitor window?
My Code:
#include "fsl_debug_console.h"
#include "fsl_device_registers.h"
#include "pin_mux.h"
#include "clock_config.h"
#include "board.h"
#include "fsl_semc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define EXAMPLE_SEMC SEMC
#define EXAMPLE_SEMC_START_ADDRESS (0x90000000U)
#define EXAMPLE_SEMC_START_ADDRESS_TX (0x900000A0U)
#define EXAMPLE_SEMC_START_ADDRESS_RX (0x900000B0U)
#define EXAMPLE_SEMC_CLK_FREQ CLOCK_GetFreq(kCLOCK_SemcClk)
#define SEMC_EXAMPLE_DATALEN 16//(0x1000U)
#define SEMC_EXAMPLE_WRITETIMES (1000U)
/*******************************************************************************
* Prototypes
******************************************************************************/
extern status_t BOARD_InitSEMC(void);
/*******************************************************************************
* Variables
******************************************************************************/
uint32_t sram_writeBuffer[SEMC_EXAMPLE_DATALEN];
uint32_t sram_readBuffer[SEMC_EXAMPLE_DATALEN];
/*******************************************************************************
* Code
******************************************************************************/
void SEMC_SRAMWrite32Bit_TXDREG(void);
void SEMC_SRAMRead32Bit_RXDREG(void);
status_t BOARD_InitSRAM(void)
{
semc_config_t config;
semc_sram_config_t sram_config;
uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ;
/* Initializes the MAC configure structure to zero. */
memset(&config, 0, sizeof(semc_config_t));
memset(&sram_config, 0, sizeof(semc_sram_config_t));
/* Initialize SEMC. */
SEMC_GetDefaultConfig(&config);
config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */
SEMC_Init(SEMC, &config);
//config SRAM
sram_config.cePinMux = kSEMC_MUXA8; // SEMC_ADDR08 is CE0# (IOCR[MUX_A8])
sram_config.address = SRAM_BASE; // Base address 0x90000000 (BR6[BA])
sram_config.memsize_kbytes = 0x10000; // SRAM0 space size 64MB (BR6[MS])
sram_config.addrPortWidth = 8; // Port width (SRAMCR0[COL]) Don't care in SRAM.
sram_config.advActivePolarity = kSEMC_AdvActiveLow; // ADV# polarity (SRAMCR0[ADVP]) Don't care if not use ADV.
sram_config.addrMode = kSEMC_AddrDataNonMux; // Non Mux mode (SRAMCR0[AM])
sram_config.burstLen = kSEMC_Nor_BurstLen1; // Burst length (SRAMCR0[BL])
sram_config.portSize = kSEMC_PortSize16Bit; // Port size 16bit (SRAMCR0[PS])
sram_config.syncMode = kSEMC_SyncMode; // ASYNC mode (SRAMCR0[SYNCEN])
//sram_config.waitEnable = true; // WAIT enable (SRAMCR0[WAITEN])
//sram_config.waitSample = 0; // WAIT sample (SRAMCR0[WAITSP])
//sram_config.advLevelCtrl = kSEMC_AdvHigh; // ADV# level control (SRAMCR0[ADVH]) Don't care if not use ADV.
sram_config.tCeSetup_Ns = 20; // CE# setup time [nsec] (SRAMCR1[CES]) Need tuning.
sram_config.tCeHold_Ns = 20; // CE# hold time [nsec] (SRAMCR1[CEH]) Need tuning.
sram_config.tCeInterval_Ns = 20; // CE# interval time [nsec] (SRAMCR2[CEITV]) Need tuning.
sram_config.readHoldTime_Ns = 20; // Read hold time [nsec] (SRAMCR2[RDH]) Only for SYNC mode.
sram_config.tAddrSetup_Ns = 20; // ADDR setup time [nsec] (SRAMCR1[AS]) Need tuning.
sram_config.tAddrHold_Ns = 20; // ADDR hold time [nsec] (SRAMCR1[AH]) Need tuning.
sram_config.tWeLow_Ns = 20; // WE low time [nsec] (SRAMCR1[WEL]) Need tuning.
sram_config.tWeHigh_Ns = 20; // WE high time [nsec] (SRAMCR1[WEH]) Need tuning.
sram_config.tReLow_Ns = 20; // RE low time [nsec] (SRAMCR1[REL]) Need tuning.
sram_config.tReHigh_Ns = 20; // RE high time [nsec] (SRAMCR1[REH]) Need tuning.
sram_config.tTurnAround_Ns = 20; // Turnaround time [nsec] (SRAMCR2[TA]) Need tuning but don't set it to be 0.
sram_config.tAddr2WriteHold_Ns = 20; // Address to write data hold time [nsec] (SRAMCR2[AWDH]) Need tuning.
sram_config.tWriteSetup_Ns = 20; // Write Data setup time [nsec] (SRAMCR2[WDS]) Only for SYNC mode.
sram_config.tWriteHold_Ns = 20; // Write Data hold time [nsec] (SRAMCR2[WDH]) Only for SYNC mode.
sram_config.latencyCount = 20; // Latency count (SRAMCR2[LC]) Only for SYNC mode.
sram_config.readCycle = 20; // read time (SRAMCR2[RD]) Only for SYNC mode.
//sram_config.delayChain = 20; // typically not used in SRAM. (DCCR [SRAMXVAL], DCCR [SRAMXEN], DCCR [SRAM0VAL], DCCR [SRAM0EN])
return SEMC_ConfigureSRAM(SEMC, &sram_config, clockFrq);
}
#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
#include "fsl_cache.h"
#endif
int main(void)
{
/* Hardware initialize. */
BOARD_ConfigMPU();
BOARD_InitBootPins();
BOARD_InitBootClocks();
CLOCK_InitSysPfd(kCLOCK_Pfd2, 29);
CLOCK_SetMux(kCLOCK_SemcMux, 1);
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
BOARD_InitDebugConsole();
if (BOARD_InitSRAM() != kStatus_Success)
{
PRINTF("\r\n SEMC SRAM Init Failed\r\n");
}
SEMC_SRAMWrite32Bit_TXDREG();
return 0;
}
void SEMC_SRAMWrite32Bit_TXDREG(void)
{
uint32_t index;
uint32_t datalen = SEMC_EXAMPLE_DATALEN;
uint32_t *sram = (uint32_t *)EXAMPLE_SEMC_START_ADDRESS;
for (index = 0; index < datalen; index++)
{
sram[index] = index * 2;
}
}
Thanks and Regards.
