I.MX RT1024 - Accessing SDRAM and SRAM in the same design, pin usage verification

[bridgenet]

In our RT1024 design we need to access SDRAM using the circuit design from the EVKMIMXRT1024 development board and also a small ASYNC 4K X 16 Dualport SRAM.  Given the way pins are multiplexed it is confusing as to how well this is supported given there is no application note.  I am assuming based on the memory address range the pin is redefined based on region.  For example for this to work SDRAM SEMC_BA1 as it is accessed and would become SRAM ADV# when it is accessed, SDRAM SEMC_A11 would become SRAM /WE, SDRAM SEMC_A12 would become SRAM /OE.  GPIO_EMC_40 would be SRAM /CS and the development board ENET_MDIO would move to GPIO_SD_B0_02.  SEMC_RDY can be connected to SRAM /Wait.  SEMC_DATA15 to SEMC_DATA00 is SDRAM D15 to D0 during its access and with SRAM it is D15/A15 to D0/A0 multiplexed and address latched with ADV# in ADMUX mode.

Is the above correct that once the Registers are initialized the pins can be connected to both the SDRAM and SRAM and operate as described?  Region  #0 for SDRAM and Region #6 for SRAM.  Does refresh of SDRAM cause any issues (using same chip as on RT1024 development board)?  Just trying to verify prior to actually doing PCB layout.

Thanks,

Kev

[jingpan]

Hi @bridgenet ,

Please refer to table 25-6 in reference manual for how to connect SRAM. SRAM and SDRAM has different #CS. SEMC.IOCR register control which CSX signals are used as SDRAM CS or SRAM CS.

Regards,

Jing

[bridgenet]

Hi Jing,

I did refer to that section of the manual and that is where the information came from.  I am looking for confirmation that what I have listed is interpreted correctly and will work correctly for using both SDRAM and SRAM at the same time.  The manual is not correct in some sections for example the address lines when addressing the SRAM in 8 bit mode are not SEMC_D8-D15 but SEMC_A8 to SEMC_A15 per a note on this forum.  The manual does not provide much information when using two different types of memory devices with the same connections.  For example SEMC_BA0 is an output for SDRAM but listed that it can be the WAIT line for SRAM which is an input, which I am not sure is correct?

Thanks,

Kev

[jingpan]

Hi @bridgenet ,

Yes, I see the report too. In new RT1020/RT1050/RT1060 RM, 8bit SRAM is no longer supported. There is lot of problem, for example, it only has 17-bit address line. It's better to use FLEXIO instead of SEMC to access 8bit SRAM.

Regards,

Jing

[bridgenet]

We will be using 16 bit access.  The 8 bit access was just a reference to where there is confusion in the manual.  Where I need clarification is on how the pins are multiplexed and when.  For example SEMC_BA0 is listed as being used for SDRAM, which is an output, but with SRAM it is WAIT, which is an input  (I listed SEMC_RDY in my original posting but that was in error as it should have been SEMC_BA0).  The manual lacks sufficient information where it should really show an example of how the lines reconfigure themselves with a clock diagram.  Since it doesn’t we need additional input to verify our understanding is correct before we proceed with a PCB layout.  For example SEMC_BA1 is bank address with the SDRAM, at what point does it become ADV# which is used to latch the address portion of the multiplexed address/data bus?  The same for SDRAM SEMC_A11, it is an address line for the SDRAM and could be high or low, at what point does it become the SRAM low level active write line.  SEMC_A11 could be low when accessing the SDRAM so at some point it would have to return high and then transition low again when accessing SRAM probably qualified with a chip select.  If there was documentation in the manual that said a certain number of clock cycles prior to the chip select of a different region all the lines reconfigure themselves for the different memory type it would clarify a lot of things.  Any information in that regard would be appreciated.

Thanks,

Kev

[jingpan]

Hi @bridgenet ,

I haven't such timing diagram. But I think this is not a problem.  The pin functions are controlled by SDRAM and SRAM controller and different time slot. They will not conflict with each other. #CE can cover its function. I mean when SDRAM #CS is asserted, these pins are controlled by SDRAM controller. When SRAM #CE is asserted, they are controlled by SRAM controller. When #CS or #CE isn't assert, SDRAM or SRAM will not take other signals.

Please don't worry about that. RT10xx SEMC can connect to both SDRAM and SRAM or even more device. SEMC won't access them simultaneously. Every memory device has been assigned different address range. MCU can't access two address via SEMC at same time. At any point in time, only one /CS can assert. So, at any point in time, SEMC pins are controlled in a dedicated function group.

Regards,

jing

[bridgenet]

Thank you Jing, let me ask this a different way and see if there is information:

A simpler question would be how many clock cycles prior to the chip select of a different memory region type does a signal on the SEMC change definition?  For example SDRAM SEMC_A11 becomes SRAM /WE (write enable), but when?  It is something that really should be in the manual as it helps when doing hardware design.  

Thanks,

Kev

[jingpan]

Hi @bridgenet ,

It need 2 SEMC clock.

Regards,

Jing