How to configure SDRAM arbitration priority between Cortex M4 and CortexM7 in IMXRT1170

[anasnadukkandiyil]

We have an LCD GUI on cortex M7 which runs lcdv2_alpha_cm7 example. LCD has frame buffer from SDRAM.

We also have a NONCAHCABLE share memory in SDRAM to share sensor values between cortex M4 and M7.

It is observed that during LCD refresh cortex M4 SDRAM access is blocked and overall cortex M4 is freeze during that time frame.

Because of memory constraints only SDRAM can be used for share memory between cores.

Our requirement is Cortex M4 need to write 1KB of data every 16ms and that access should be given arbitration priority than LCD framebuffer update in cortex M7.

[Kan_Li]

Hi @anasnadukkandiyil ,

Bus Master Control Registers (BMCRn) Configuration can be used for that purpose, but better you put the memory shared between M7 and M4 in the following space:

Have a great day,
Kan

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