what is imx8 core base for jtag ~~Help

[fatalfeel]

for jtag openocd

I get BSDL file for i.MX 8M (REV 1)  

it's 0x1cf80553 for sjc_tapid

# System JTAG Controller
if { [info exists SJC_TAPID] } {
        set _SJC_TAPID $SJC_TAPID
} else {
        set _SJC_TAPID 0x1cf80553
}
set _SJC_TAPID2 0x2cf80553

jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
        -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2

now i.mx8

1. need Base addresses of cores

2. CoreSight Debug Access Port

///////////////////////////////////////////////////////////////////////

this is for arm arch64

///////////////////////////////////////////////////////////////////////

set _cores 8
for { set _core 0 } { $_core < $_cores } { incr _core 1 } {

    set _command "target create ${_TARGETNAME}$_core aarch64 \
                         -chain-position $_CHIPNAME.dap -coreid $_core -ctibase [set $_TARGETNAME.cti($_core)]"

    if { $_core != 0 } {
        # non-boot core examination may fail
        set _command "$_command -defer-examine"
        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
    } else {
        # uncomment when "hawt" rtos is merged
        # set _command "$_command -rtos hawt"
        set _smp_command "target smp ${_TARGETNAME}$_core"
    }

    eval $_command
}

eval $_smp_command

# declare the auxiliary Cortex-M3 core on AP #2 (runs mcuimage.bin)
target create ${_TARGETNAME}.m3 cortex_m -chain-position $_CHIPNAME.dap -ap-num 2 -defer-examine

///////////////////follow is for imx.6 info ///////////////////

# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
        set _DAP_TAPID $DAP_TAPID
} else {
        set _DAP_TAPID 0x4ba00477
}

jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
        -expected-id $_DAP_TAPID

# SDMA / no IDCODE
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f

# System JTAG Controller
if { [info exists SJC_TAPID] } {
        set _SJC_TAPID $SJC_TAPID
} else {
        set _SJC_TAPID 0x0191c01d
}
set _SJC_TAPID2 0x0191e01d
set _SJC_TAPID3 0x2191c01d
set _SJC_TAPID4 0x2191e01d

jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
        -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \
        -expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4

# GDB target: Cortex-A9, using DAP, configuring only one core
# Base addresses of cores:
# core 0  -  0x82150000
# core 1  -  0x82152000
# core 2  -  0x82154000
# core 3  -  0x82156000
set _TARGETNAME $_CHIPNAME.cpu.0
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
        -coreid 0 -dbgbase 0x82150000

[fatalfeel]

openocd-0.10.1.tar.gz in github

https://github.com/fatalfeel/openocd_integrated 

[ranjith_tc]

Hi Jesse stone,

Do you know the coresight base address for iMX8QMax(4 x A53+2 x A72)?

[fatalfeel]

maybe same as imx8

need try ex:  like
# core 0  -  0x80A10000 / cti - 0x80A420000

[ranjith_tc]

Okay. Thanks. Let me try that.

But I got reply from NXP support team that for this processor, the access to debug components is via a secure module.

So, do you know, how to do that?

[fatalfeel]

jtag openocd eclipse

see the imx8m.cfg setting will give you answer
ver 0.10.1 test compile ok on ubuntu 16.04 x64
made on march 2020
http://fatalfeel.blogspot.com/2015/12/openocd-with-eclipse-debug-kernel-of.html

[fatalfeel · Accepted solution]

# Freescale i.MX8 series single/dual/quad core processor

if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
} else {
   set  _CHIPNAME imx8
}

# Debug Access Port
if { [info exists DAP_TAPID] } {
        set _DAP_TAPID $DAP_TAPID
} else {
        set _DAP_TAPID 0x5ba00477
}

jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
        -expected-id $_DAP_TAPID

# SDMA / no IDCODE
#jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f

# SOC JTAG ID / IDCODE refer to BSDL file
#if { [info exists SJC_TAPID] } {
#        set _SJC_TAPID $SJC_TAPID
#} else {
#        set _SJC_TAPID 0x1cf80553
#}
#set _SJC_TAPID1 0x2cf80553

#jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
        -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID1

# GDB target: Cortex-A53, using DAP, configuring only one core
# Coresight base address:
# core 0  -  0x80410000 / cti - 0x80420000
# core 1  -  0x80510000 / cti - 0x80520000
# core 2  -  0x80610000 / cti - 0x80620000
# core 3  -  0x80710000 / cti - 0x80720000
set _TARGETNAME $_CHIPNAME.cpu0
#set _TARGETNAME_1 $_CHIPNAME.cpu1
#set _TARGETNAME_2 $_CHIPNAME.cpu2
#set _TARGETNAME_3 $_CHIPNAME.cpu3

target create $_TARGETNAME aarch64 -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x80410000 -ctibase 0x80420000
#target create $_TARGETNAME_1 aarch64 -chain-position $_CHIPNAME.dap -coreid 1 -dbgbase 0x80510000 -ctibase 0x80520000
#target create $_TARGETNAME_2 aarch64 -chain-position $_CHIPNAME.dap -coreid 2 -dbgbase 0x80610000 -ctibase 0x80620000
#target create $_TARGETNAME_3 aarch64 -chain-position $_CHIPNAME.dap -coreid 3 -dbgbase 0x80710000 -ctibase 0x80720000
        
# some TCK cycles are required to activate the DEBUG power domain
#jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"

proc imx8_dbginit {target} {
        # General Cortex-A53 debug initialisation
        aarch64 dbginit
}

# Slow speed to be sure it will work
adapter_khz 1000
$_TARGETNAME configure -event reset-start { adapter_khz 1000 }

$_TARGETNAME configure -event reset-assert-post "imx8_dbginit $_TARGETNAME"
$_TARGETNAME configure -event gdb-attach { halt }

[fatalfeel]

openocd 2018 03 01 merge and update jaylink deiver

search key word ->  openocd-0.10.0_v13.tar.gz  and download

http://fatalfeel.blogspot.tw/2015/12/openocd-with-eclipse-debug-kernel-of.html

./configure --prefix=/opt/openocd --enable-maintainer-mode --enable-ftdi --enable-target64
make && make install

find -> imx8.cfg  //done

[fatalfeel]

Finding JTAG on Odroid-C2 | MOV r0 

bcm2837.cfg · GitHub 

http://codegist.net/code/bcm2837/ 

Bare Metal Debug - HiKey - 96Boards 

i found  crotex-a53 cores addr param here

[diegoadrian]

I apologize for the delay.

But, what is exactly your question?

Best Regards,

Diego.

[fatalfeel]

1. Base addresses of cores of imx8

2. CoreSight Debug Access Port of imx8

///////////////////////

ex:

base address of core of imx6 is 0x82150000

CoreSight Debug Access Port of imx6 is 0x4ba00477

[diegoadrian]

Hello,

Everything related to the cortex you can see it in the ARM documentation. For example, you can see on the below link the reference manual for the ARM cortex A-53, there are located the base address of the cortex.

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500d/DDI0500D_cortex_a53_r0p2_trm.pdf 

I hope this can help you,

Best Regards,

Diego.