imx8qm IRQSTEER interrupt mapping

[thierry_durand]

Hi all,

I'm confused about how the interrupt sources are mapped to the IRQSTEER. Here is a use case to illustrate:

I want the M4_0 to use LSIO GPT_4. The interrupt ID of GPT_4 is 167. I could experimentally figure out that this interrupt source #167 is routed to IRQSTEER_1 and becomes vector 33 to the M4 core. But how I derive 33 from 167?

I'd appreciate it if someone could elaborate on the process or point me to relevant documentation.

Thanking you in advance,

--

TD

[igorpadykov]

Hi Thierry

M4 has it's own NVIC, table below (it is from i.MX8QXP Reference Manual,

but for i.MX8QM it is the same) shows "external interrupt" vectors -
"external" interrupts are mapped to IRQSTEER module, so  
IRQSTEER_1 becomes vector 33 to the M4 core.

i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual

Best regards
igor
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[thierry_durand]

That's interesting, thank you, Igor.

So the interrupt triggered by GPT_4 is routed to IRQSTEER_1, which then triggers interrupt 33 of the M4, as described in the table you mentioned. Do I get it correctly?

Now the question is: how comes GPT_4 is associated to IRQSTEER_1?

Thank you for your patience.

--

TD

[igorpadykov]

I sent additional details via mail.

Best regards
igor

[GVVV]

can you provide this information to me as well? I am having an issue figuring out which IRQ_STEER the Flexcan interrupts are routed too.

[qingjun]

1. as these description,  

 LSIO_GPIO_INT7_IRQn is 168. 

 LSIO_MU5_INT_B_IRQn is 183. 

these two interrupt source are  corresponding  to IRQSTEER_2_IRQn = 34, /**< External interrupt 2 */.

but now 168  is IRQSTEER_1,    183 is IRQSTEER_2. could you help figure out the relationship?

2.  the NVIC only support 0-255 number interrupt, except for 16 core interrupt, there have 240 number interrupt, which is corresponding the code description.

         __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */

but the external interrupt source is 384,  is there have the description for the relationship fir the  NVIC and external interrupt source ? now i am confused with the relationship among Shared Int Source, NVIC, and IRQ_STEER, could you have a instance for this?

thank you  

[qingjun]

Could you please elaborate ?

i working on iMX8DXL-M4, Recently encountered the same problem。

Please consider the following source code:

        GPIO_PortEnableInterrupts(LSIO__GPIO7, 1 << bPinNum);

        NVIC_EnableIRQ(IRQSTEER_1_IRQn);

        NVIC_SetPriority(IRQSTEER_1_IRQn, 6);

        IRQSTEER_EnableInterrupt(IRQSTEER, LSIO_GPIO_INT7_IRQn);

i have experiment this code is ok. I found out that M4 receives IRQSTEER_1 (which is 33) whereas LSIO_GPIO_INT7_IRQn is 168. 

          NVIC_SetPriority(IRQSTEER_2_IRQn, 3);

          IRQSTEER_EnableInterrupt(IRQSTEER, LSIO_MU5_INT_B_IRQn);

M4 receives IRQSTEER_2 (which is 34) whereas LSIO_MU5_INT_B_IRQn is 183. 

Is there a way to figure out the relation between the IRQ fired by the peripheral and the IRQSTEER_n_IRQn (n ranging from 0 to 5) ? i can't find these description in specific document.

thanks a lot for helping,

[bruno_aubert]

Hi Igor,

Could you please elaborate ?

Please consider the following source code:

        IRQSTEER_EnableInterrupt(IRQSTEER, LSIO_GPT0_INT_IRQn);

        /* priority has to be higher or equal to 2, to meet FreeRTOS requirements */

        NVIC_SetPriority(IRQSTEER_1_IRQn, 2);

This code is ok. I found out that M4.0 receives IRQSTEER_1 (which is 33) whereas LSIO_GPT0_INT_IRQn is 163. But this a generic code for GPTs, so I don't want IRQSTEER_1_IRQn to be hard-coded. What if I use AUDIO_GPT1 ?

Is there a way to figure out the relation between the IRQ fired by the peripheral and the IRQSTEER_n_IRQn (n ranging from 0 to 7) ?

thanks a lot for helping,

Bruno.

[igorpadykov]

Hi Bruno

>Is there a way to figure out the relation between the IRQ fired by the peripheral
>and the IRQSTEER_n_IRQn (n ranging from 0 to 7) ?

IRQSTEER_0  External Interrupt 0  IRQ=32  (Ints 0-63 from Table 3-4. Shared Peripheral Interrupts)
IRQSTEER_1  External Interrupt 1  IRQ=33 (Ints 64-127 from Table 3-4. Shared Peripheral Interrupts)
...
e.t.c.

Best regards
igor

[bruno_aubert]

Hi Igor,

Thanks for this usefull reply. 

As I struggle to get the full picture on how IRQSTEER works, I have 2 others questions.

1. I have a document stating "IRQ Channel : Channel #1, IRQ_STEER out [15:8] : destination is CM4 #0". First I thought all interrupts directed to CM4#0 used IRQSTEER_1, because of "Channel #1". Now I think there is no relationship between channel 1 and IRQSTEER_1. Am I right ?
2. IRQSTEER_1 is used for GPT0..GPT4 (I found out with a debugger). From your previous answer, IRQSTEER_1 is used for IRQ 64-127. The table "shared peripheral interrupts" in iMX8QM documentation has 112.116 for these peripherals, so it seems easy. But the BSP defined IRQ for GPT0..GPT4 as 163..167. Is the range 112..116 the range from the GIC point of view ? I can't find #define for these values in the BSP. Can you confirm that IRQSTEER is based on IRQ listed in this table ?

Your help is greatly appreciated,

Regards,

Bruno.

[igorpadykov]

Hi Bruno

additional details were sent to your support case 00283135.

Best regards
igor

[emolina-ebers]

Could you make this response public?

I have the same question.

There are 594 IRQn in MIMX8QX6_cm4.h, while only IRQ_Steer manages 512.

For example I can't see how is related IRQSTEER_2_IRQn with LSIO_GPIO_INT1_IRQn