imx8mp with DDR4 cannot jump to U-boot

[Takahiro_wt]

Dear i.MX u-Boot Experts,

Our custom board using i.mx8M Plus + DDR4 cannot jump to U-boot.

SPL Stucks at calling function pointer 0x970000. It seems to missing a BL31 image.

No log is appear after "image entry point: 0x970000".

Please teach me which source code shoud be modified.

Memory devices on our board are MT40A512M16-062E/IT:R
I had modified arch/arm/dts/imx8mp-evk.dts of u-boot-imx as below but didn't work well.

memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};

===============================================

[Our board]

===============================================

>>SPL: board_init_r()
using memory lx-lx for malloc()
spl_init
0
- 0 'pinctrl@30330000'
- found
caam_jr crypto@30900000: set_state_simple op missing
clk_set_defaults(crypto@30900000)
clk_set_default_parents: could not read assigned-clock-parents for 95ef60
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_addr_size_auto_parent: na=1, ns=1, fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32_index: reg: x (8192)
01: operation
02: jump
03: load_imm_u32
05: operation
00000000: No error:
01: operation
00000000: No error:
SEC0: RNG instantiated
Trying to boot from BOOTROM
Boot Stage: Recovery boot
image offset 0x8000, pagesize 0x200, ivt offset 0x0
spl_romapi_raw_seekable_read 0x60000, size 0x600
fit read sector 300, sectors=3, dst=422001d0, count=3, size=0x430
no IVT header found
board_fit_config_name_match: evkddr4
Selecting config 'evkddr4'
firmware: 'uboot-1'
spl_romapi_raw_seekable_read 0x63000, size 0x13e000
External data: dst=40200000, offset=3000, size=13de58
Can't get 'entry' property from FIT 0x422001d0, node: offset 104, name uboot-1 (FDT_ERR_NOTFOUND)
fdt: 'fdt-1'
Can't get 'load' property from FIT 0x422001d0, node: offset 260, name fdt-1 (FDT_ERR_NOTFOUND)
spl_romapi_raw_seekable_read 0x1a0e00, size 0xce00
External data: dst=4033de80, offset=140e58, size=cc18
Can't get 'entry' property from FIT 0x422001d0, node: offset 260, name fdt-1 (FDT_ERR_NOTFOUND)
loadables: 'atf-1'
spl_romapi_raw_seekable_read 0x1ada00, size 0xb200
External data: dst=970000, offset=14da70, size=b150
loadables: 'tee-1'
spl_romapi_raw_seekable_read 0x1b8a00, size 0x7d200
External data: dst=56000000, offset=158bc0, size=7cfa0
no string for index 2
fdtdec_get_int_array: start-config
get_prop_check_min_len: start-config
fdtdec_get_int_array: stop-config
get_prop_check_min_len: stop-config
Jumping to U-Boot...
image entry point: 0x970000

===============================================

[8MPLUSLPD4-EVK]

===============================================

>>SPL: board_init_r()
using memory lx-lx for malloc()
spl_init
0
- 0 'pinctrl@30330000'
- found
caam_jr crypto@30900000: set_state_simple op missing
clk_set_defaults(crypto@30900000)
clk_set_default_parents: could not read assigned-clock-parents for 95ef60
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_addr_size_auto_parent: na=1, ns=1, fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32_index: reg: x (8192)
01: operation
02: jump
03: load_imm_u32
05: operation
00000000: No error:
01: operation
00000000: No error:
SEC0: RNG instantiated
Normal Boot
Trying to boot from BOOTROM
Boot Stage: Primary boot
image offset 0x8000, pagesize 0x200, ivt offset 0x0
spl_romapi_raw_seekable_read 0x60000, size 0x600
fit read sector 300, sectors=3, dst=422001d0, count=3, size=0x428
no IVT header found
board_fit_config_name_match: evk
Selecting config 'evk'
firmware: 'uboot-1'
spl_romapi_raw_seekable_read 0x63000, size 0x12e400
External data: dst=40200000, offset=3000, size=12e400
Can't get 'entry' property from FIT 0x422001d0, node: offset 104, name uboot-1 (FDT_ERR_NOTFOUND)
fdt: 'fdt-1'
Can't get 'load' property from FIT 0x422001d0, node: offset 260, name fdt-1 (FDT_ERR_NOTFOUND)
spl_romapi_raw_seekable_read 0x191400, size 0xca00
External data: dst=4032e400, offset=131400, size=c9b0
Can't get 'entry' property from FIT 0x422001d0, node: offset 260, name fdt-1 (FDT_ERR_NOTFOUND)
loadables: 'atf-1'
spl_romapi_raw_seekable_read 0x19dc00, size 0xb400
External data: dst=970000, offset=13ddb0, size=b150
loadables: 'tee-1'
spl_romapi_raw_seekable_read 0x1a8e00, size 0x7d200
External data: dst=56000000, offset=148f00, size=7cfa0
no string for index 2
fdtdec_get_int_array: start-config
get_prop_check_min_len: start-config
fdtdec_get_int_array: stop-config
get_prop_check_min_len: stop-config
Jumping to U-Boot...
image entry point: 0x970000
NOTICE: BL31: v2.6(release):lf-5.15.71-2.2.2-0-gf4540f956
NOTICE: BL31: Built : 06:10:48, Apr 13 2023
initcall: 00000000402bc01c

U-Boot 2022.04-lf_v2022.04+g181859317b (Nov 15 2022 - 06:28:05 +0000)

initcall: 000000004022acec
U-Boot code: 40200000 -> 4032E400 BSS: -> 40343C88

[Takahiro_wt]

Thank you so much.

It seems that there is problen in UART setting, so we've trying the UART port num implementation.

Because:

- We had changed UART port setting to UART3. The topic below was same situation.

https://community.nxp.com/t5/i-MX-Processors/IMX8MP-uart2-to-uart4/m-p/1616936

- We had tried with the board replaced memory devices to MT40A1G16 which is same to DDR4-EVK, and it had stopped in the same place.

Regards,

[Bio_TICFSL]

Hello,

There are multiple things you need to take into consideration when using the A53 processor to execute multiple applications on different exception levels.

1. Your application needs to written to target the appropriate exception level. The boot code provided by the BSP used by the application is accessing specific processor registers that are associated to different exception levels. As by default your application is targeting EL3, if at runtime is being executed at less privileged EL (i.e. EL2), the access to the EL3 register will generate an exception. In Vitis or SDK, there is an option to change the exception level of your BSP code from EL3 to EL1 enabling the hypervisor_guest option.
2. Boot process of the applications. The software stack is build in a way that you start executing from the higest privileged level (EL3) and then going down to the different levels. shoud jump to ATF and ATF should jump to your application.  Note that there is an assumption that the entry point will not be 0x0, so ensure that's the case also for your application.

I just tested on my side using 6.6.3 release of the tools and following the next steps.

• Create a platform in your uboot with a domain targeting the A53 processor
• Modify the BSP of the A53 domain and enable the hypervisor_guest option to target EL1 exception level
• Run the ddr stress test

Regards