Hello All,
I’m using ring buffer with lock free design to transmit some data from one core to another.
My testing code is using three constant data arrays as the souce data, first is 1520 bytes all with value 0x11, second is 64 bytes all with value 0x22 , third is 64 bytes all with value 0x33. There are 128 ring buffers. one core will copy each array into buffer, and set widx increase ,at meantime another core will polling and compare widx and ridx, if there is new data put in, it will copy the data to the local buffer, and check if get the wrong data.
I found it has a chance to receive the third array data mixed with the data in first array.
The widx, ridx and each ring buffer are already alignment with 64bytes, and using __asm__ __volatile__("": : :"memory") to make sure “widx ++” after all data have been copied into ring buffer, thus I think may be there is coherence issue.
The testing is also running on evk board (kernel 5.4 image download from nxp website)
Output hex:
0000 33 33 33 33 33 33 33 33 11 11 11 11 11 11 11 11
0010 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
0020 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
0030 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
