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iMX8MP Ethernet DeviceTree configuration

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iMX8MP Ethernet DeviceTree configuration

‎04-11-2024 04:46 AM
421 Views
ChristianD
Contributor I

We use a i.MX8MP processor and connect both ethernet (fec, and qos). Unfortunately, we forgot to put pull-up resistors on both `INT` and `RX_CTL` signals in between CPU and the ETH controller chip.

Now, after starting Linux (rightfully) complains "mdio_bus stmmac-1: MDIO device at address 3 is missing.", same for the other one. After measuring the INT pins, they show 1.7V and 1.2V, respectively. Also, the LED at the RJ45 port is off.

Apart from soldering in a pull-up resistors, we thought about setting the pins on the CPU side in the devicetree file of Linux to (weak) pull-up, but were unsuccessful so far.

Here is an Devicetree file example that works (with hardware pull-up resistors):

 

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_fec_phy>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
			ti,dp83867-rxctrl-strap-quirk;
			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
			reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
			reset-assert-us = <500000>;
			reset-deassert-us = <50000>;
			enet-phy-lane-no-swap;
			interrupt-parent = <&gpio4>;
			interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
			/* LED0: Link, LED2: activity */
			ti,led-function = <0x0100>;
			/* LED0/2: active High, driven by phy function */
			ti,led-ctrl = <0x1414>;
		};
	};
};


...

&gpio4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio4>;

	gpio-line-names =
		"ENET0_RST", "ENET0_INT", "ENET1_RST", "ENET1_INT",
		...;
	enet0-int-hog {
		gpio-hog;
		gpios = <1 0>;
		input;
		line-name = "ENET0_INT";
	};

	enet1-int-hog {
		gpio-hog;
		gpios =  0>;
		input;
		line-name = "ENET1_INT";
	};


...

	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC          0x40000044
			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO         0x40000044
			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0    0x00000090
			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1    0x00000090
			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2    0x00000090
			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3    0x00000090
			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC     0x00000090
			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x00000090
			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0    0x00000012
			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1    0x00000012
			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2    0x00000012
			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3    0x00000012
			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x00000012
			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC    0x00000014
		>;
	};

	pinctrl_fec_phy: fecphygrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06         0x00000084
			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07         0x00000084
			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00         0x00000084
			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01          0x00000084
		>;
	};

 

 

According to the reference manual of the processor, we changed:

 

...
			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RX_CTL     0x000001D0
...
			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01          0x000001C4

 

 which should set PUE_1_WEAK_PULL_UP and PE_1_PULL_ENABLE, yet with no success. Does it have to be specified somewhere else?

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2 Replies

‎04-11-2024 03:11 PM
383 Views
JosephAtNXP
NXP TechSupport
NXP TechSupport

RX_CTL doesn't require a pull-up, you can focus on RST and INT.

 

Try with this device tree:

 

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_fec_phy>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
			ti,dp83867-rxctrl-strap-quirk;
			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
			reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
			reset-assert-us = <500000>;
			reset-deassert-us = <50000>;
			enet-phy-lane-no-swap;
			interrupt-parent = <&gpio4>;
			interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
			/* LED0: Link, LED2: activity */
			ti,led-function = <0x0100>;
			/* LED0/2: active High, driven by phy function */
			ti,led-ctrl = <0x1414>;
		};
	};
};


...

&gpio4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio4>;

	gpio-line-names =
		"ENET0_RST", "ENET0_INT", "ENET1_RST", "ENET1_INT",
		...;
	enet0-int-hog {
		gpio-hog;
		gpios = <1 0>;
		input;
		line-name = "ENET0_INT";
	};

	enet1-int-hog {
		gpio-hog;
		gpios =  0>;
		input;
		line-name = "ENET1_INT";
	};


...

	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC          0x2
			/* In case MDIO doesn't have a pull up, otherwise 0x2 */
			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO         0x142
			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0    0x00000090
			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1    0x00000090
			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2    0x00000090
			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3    0x00000090
			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC     0x00000090
			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x00000090
			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0    0x00000012
			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1    0x00000012
			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2    0x00000012
			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3    0x00000012
			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x00000012
			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC    0x00000012
			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO01         0x150
		>;
	};

	pinctrl_fec_phy: fecphygrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06         0x00000084
			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07         0x00000084
			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO00          0x00000084
		>;
	};

 

Why are GPIO 2-6, 2-7 and 4-0 used for?

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‎04-12-2024 12:55 AM
367 Views
ChristianD
Contributor I

GPIO4-0 is connected to ENET_RST, GPIOs 2-6 and -7 are some extended run-time configuration and status info bits (https://www.ti.com/lit/gpn/DP83867IS GPIO_MUX_CTL register has more details)

On a side note: you were right with your suspicion on the MDIO. The pullups were forgotten there, too. Kudos!

I tried your modifications (including the MDIO pullup), but to no avail. The ENET_RST on GPIO4-0 I did not modify since this guy has a HW pullup resistor on it. After modifications to the Linux devicetree, even the RJ45 LEDs stays disabled. Is it maybe required to also do these modifications for uboot devicetree files?

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