iMX8M Nano DDR Calibration

[afar89]

We have a board designed around iMX8M Nano, similar to EVK. There is a single x16 DDR4 chip (AS4C512M16D4-75BCN). PMIC is BD71850.

We're able to run the Mscale DDR Tool and download our ds script (attached) successfully. Running "Calibration" the tool seems stuck at 1D-Training. We've run this at 800MHz and 1000MHz. I've verified that all rails are within spec and there is no voltage dip when calibration is started. I've let it run for 15 minutes with no change.

Can you please help me figure out why the training sequence is stuck at the first step?

Download is complete
Waiting for the target board boot...

===================hardware_init=====================

********Found PMIC BD718XX**********
hardware_init exit

*************************************************************************

*************************************************************************

*************************************************************************
       MX8 DDR Stress Test V3.10
       Built on Feb  5 2020 13:02:45
*************************************************************************

--Set up the MMU and enable I and D cache--
   - This is the Cortex-A53 core
  - Check if I cache is enabled 
  - Enabling I cache since it was disabled 
  - Push base address of TTB to TTBR0_EL3 
  - Config TCR_EL3 
  - Config MAIR_EL3 
  - Enable MMU 
  - Data Cache has been enabled 
  - Check system memory register, only for debug 

   - VMCR Check:
   - ttbr0_el3: 0x97d000
   - tcr_el3: 0x2051c
   - mair_el3: 0x774400
   - sctlr_el3: 0xc01815
   - id_aa64mmfr0_el1: 0x1122

  - MMU and cache setup complete 

*************************************************************************
            ARM clock(CA53) rate: 1000MHz
            DDR Clock: 0MHz

============================================
        DDR configuration
DDR type is DDR4
Data width: 16, bank num: 8
For DDR4, bank num is the total of 2 bank groups and 4 banks per group 
Row size: 16, col size: 10
One chip select is used 
Number of DDR controllers used on the SoC: 1
Density per chip select:   1024MB 
Density per controller is: 1024MB 
Total density detected on the board is: 1024MB 
============================================

MX8M-nano: Cortex-A53 is found

*************************************************************************

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1066Mhz...

[nxf63675]

Hi A Far,

Please share with us the programming aid sheet and the version of the tool that you are using, also if you can update the schematics and datasheet for the RAM that you are using it will be very helpful for debugging this issue.

Regards,

Israel H.

[afar89]

Thank you for following up. Attached is RPA v4 sheet used to generate the ds file. Tool version is 3.10. I'm sending you the design schematics privately. Datasheet is linked to in my original post.

Please let me know if there is anything else you need.

[nxf63675 · Accepted solution]

Hi A Far,

The issue appears to be caused by incorrect DDR clock configuration as shown in the provided log:

 DDR Clock: 0MHz

If you in the RPA change the clock frequency from 1200 MHz to a different value in the "Register Configuration" tab, you need to manually calculate and enter the correct setting for the DDR PLL configuration register in the "DDR Stress Test" tab since the RPA changes the respective value in row 44 to "TBD" when anything else than 1200 MHz is set:

memory set	0x30360054	32	TBD								

Usually, there are multiple PLL configurations that can produce the desired frequency and thus, multiple values are possible. For the desired frequencies, the following values can be chosen:

800 MHz:

memory set	0x30360054	32	0x7D060							

1000 MHz:

memory set	0x30360054	32	0x32030						

In addition, you should also pay attention to the read latency (CL) setting when changing the frequency (cell F28 in "Register Configuration" tab) and select the correct one according to the datasheet of the memory device (refer to the speed bin tables).

Note: If you modify the PLL configuration register setting directly in an already generated script and not in the RPA, then apart from row 44 you also need to put the same value to row 189 (in the RPA the value of this row automatically mirrors the one in row 44):

freq0 set	0x30360054	32	TBD

Another note would be regarding the settings of the second frequency setpoint (FREQ1 setpoint Clock Cycle Freq (MHz)). 533 MHz is only supported by DDR4 memories from Micron since this frequency goes beyond the JEDEC standard definitions. For any other vendor you should choose 668 MHz instead.

Regards,

Israel H.

[afar89]

Your suggestion fixed the problem. Thank you!