iMX6UL no data on Ethernet fec2 ENET2 MII bus

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iMX6UL no data on Ethernet fec2 ENET2 MII bus

1,180 Views
yvan
Contributor II

Hello,

We have a custom board based on Armadeus OPOS6UL module (iMX6UL) version without wifi option.
We want to connect a PLC module ont the ENET2 MII bus (already using this modules on other hardwares/processors).

The PLC module acts as a Phy except that there is no MDIO, we specify a fixed-phy 100Mb full-duplex.

Problem is:

When we send data (ARP requests, ICMP...) from iMX to PLC: nothing goes out of the PLC module.

Register ENET2_RMON_T_PACKETS[0x2028204] correctly counts the number of packet to be sent.

Register ENET2_IEEE_T_FRAME_OK[0x202824c] says that all packets has been sent OK

With a scope we can see data signals moving on ENET2_TXDATA[0-3]...

In the other direction: Wen we send broadcast data (ARP requests) on the PLC network,but the iMX sees nothing.

we can see data on ENET2_RXDATA[0-3] .

Register ENET2_RMON_R_PACKETS[0x2028284] keep counting 0 packet received.

Except if we send a lot of data, it counts a few of them in error (ENET2_IEEE_R_CRC[0x20282d0] and  ENET2_IEEE_R_ALIGN[0x20282d4]).

ENET2_RX_CLK and ENET2_TX_CLK are 25MHz.

Here is the ethernet device tree configuration:


/* ethernet 2 */
&fec2 {
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet2>;
        phy-mode = "mii";
        fixed-link {
                speed = <100>;
                full-duplex;
        };
};


&iomuxc {
        pinctrl_enet2: enet2grp {
               fsl,pins = <
                        MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x130b0 
                        MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x130b0 
                        MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x130b0 
                        MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x130b0 
                        MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x130b0 
                        MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x130b0
                        MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x130b0

                        MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
                        MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x1b0b0
                        MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
                        MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 
                        MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x1b0b0 
                        MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x1b0b0 
                        MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x4001b031 

                        MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x130b0 /* Phy to MAC */
                        MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x130b0 /* Phy to MAC */
                >;
        };
};

Does anyone have a clue or faced something similar?

Thanks in advance!

Labels (3)
8 Replies

384 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi yvan

if nothing goes out of the PLC module, seems issue in PLC module and one can

compare its signals/configuration with ones from working platform.

For fec2 dts example one can look at linux/arch/arm/boot/dts/imx6ul-14x14-evk.dts

linux-imx.git - i.MX Linux Kernel 

and test with nxp official bsps described on

https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/i.mx-6ser...

Best regards
igor
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yvan
Contributor II

Hi Igor, thanks for the quick answer!

I based my configuration on this imx6ul-14x14-evk.dts, but I have to use "MII" instead of "RMII"The PLC module is working well, data comming from PLC side are present at the output of the module on the MII bus, but iMX doesn't understand the data.There is no configuration on the PLC module except hardware pins to select 10/100 and half/full duplex. These pins are configured to 100M full-duplex.
I have read content of all ENET2_* registers (IMX6UL reference Manual chapter 22.5)ENET2_RCR.MII_MODE is set to 1
ENET2_RCR.RMII_MODE is set to 0
I can't see anything else relative to the MII.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi yvan

for mii please look at linux/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts

linux-imx.git - i.MX Linux Kernel 

Best regards
igor

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384 Views
yvan
Contributor II

Hello Igor,

I've made one step forward!

I forgot to mention that my work is based on the kernel 4.8.10 provided by Armadeus with their module.
I tried to quickly compile a minimal version of the freescale BSP 4.1.15_2.0.0 and do as less modification as possible to make it boot on my board.
It booted, but ethernet was not working.

I came back on the 4.8.10 version and noticed that the signals from imx6 to plc module on TXDATA[0-3] was too quick!
I found out that enet2 clock was fixed to 50MHz, thats good for RMII but not for MII mode.
so I changed

clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000);

to 

clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 25000000);

in drivers/clk/imx/clk-imx6ul.c

Now TxData have the good timings and ethernet frames are going through the PLC module! I can receive the frames on my computer Smiley Happy

But still nothing on receive. RXDATA[0-3] RX_CLK, RX_EN are good, but the imx6 doesn't see anything...

Any other clue?

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384 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi yvan

one can check sion bit as in

i.MX6UL ENET1 (with LAN8720A PHY) working in Uboot but not in Linux 

Best regards
igor

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384 Views
yvan
Contributor II

Thanks for your reactivity!

Il tried to enable SION bit forENET2_RX_CLK , then for all ENET2_R* pins but still the same behaviour.

I tried to disable '

fec_enet_clk_enable(ndev, false);

' like Matthew Starr did in your link, but it freezes the bootup of the kernel.

I dump all kind of registers relative to ENET2 :

ENET2_EIR[0x020b4004] = 0x00000000

ENET2_EIMR[0x020b4008] = 0x0a8080aa
ENET2_RDAR[0x020b4010] = 0x01000000
ENET2_TDAR[0x020b4014] = 0x00000000
ENET2_ECR[0x020b4024] = 0xf0000112
ENET2_MMFR[0x020b4040] = 0x00000000
ENET2_MSCR[0x020b4044] = 0x0000001a
ENET2_MIBC[0x020b4064] = 0x40000000
ENET2_RCR[0x020b4084] = 0x45f20004
ENET2_TCR[0x020b40c4] = 0x00000004
ENET2_PALR[0x020b40e4] = 0x3e23e2ef
ENET2_PAUR[0x020b40e8] = 0xf75f8808
ENET2_OPD[0x020b40ec] = 0x00010000
ENET2_TXIC[0x020b40f0] = 0xcc80080e
ENET2_RXIC[0x020b4100] = 0xcc80080e
ENET2_IAUR[0x020b4118] = 0x00000000
ENET2_IALR[0x020b411c] = 0x00000000
ENET2_GAUR[0x020b4120] = 0x20400002
ENET2_GALR[0x020b4124] = 0x00808001
ENET2_TFWR[0x020b4144] = 0x00000100
ENET2_RDSR[0x020b4180] = 0x8f048000
ENET2_TDSR[0x020b4184] = 0x8f04c000
ENET2_MRBR[0x020b4188] = 0x00000600
ENET2_RSFL[0x020b4190] = 0x00000000
ENET2_RSEM[0x020b4194] = 0x00000000
ENET2_RAEM[0x020b4198] = 0x00000004
ENET2_RAFL[0x020b419c] = 0x00000004
ENET2_TSEM[0x020b41a0] = 0x00000000
ENET2_TAEM[0x020b41a4] = 0x00000004
ENET2_TAFL[0x020b41a8] = 0x00000008
ENET2_TIPG[0x020b41ac] = 0x0000000c
ENET2_FTRL[0x020b41b0] = 0x000005f2
ENET2_TACC[0x020b41c0] = 0x00000000
ENET2_RACC[0x020b41c4] = 0x00000086
ENET2_RMON_T_DROP[0x020b4200] = 0x00000000
ENET2_RMON_T_DROP[0x020b4200] = 0x00000000
ENET2_RMON_T_PACKETS[0x020b4204] = 0x0000010b
ENET2_RMON_T_BC_PKT[0x020b4208] = 0x0000006a
ENET2_RMON_T_MC_PKT[0x020b420c] = 0x000000a1
ENET2_RMON_T_CRC_ALIGN[0x020b4210] = 0x00000000
ENET2_RMON_T_UNDERSIZE[0x020b4214] = 0x00000000
ENET2_RMON_T_OVERSIZE[0x020b4218] = 0x00000000
ENET2_RMON_T_FRAG[0x020b421c] = 0x00000000
ENET2_RMON_T_JAB[0x020b4220] = 0x00000000
ENET2_RMON_T_COL[0x020b4224] = 0x00000000
ENET2_RMON_T_P64[0x020b4228] = 0x00000042
ENET2_RMON_T_P65TO127[0x020b422c] = 0x00000013
ENET2_RMON_T_P128TO255[0x020b4230] = 0x00000054
ENET2_RMON_T_P256TO511[0x020b4234] = 0x00000060
ENET2_RMON_T_P512TO1023[0x020b4238] = 0x00000002
ENET2_RMON_T_P1024TO2047[0x020b423c] = 0x00000000
ENET2_RMON_T_P_GTE2048[0x020b4240] = 0x00000000
ENET2_RMON_T_OCTETS[0x020b4244] = 0x0000dafa
ENET2_IEEE_T_DROP[0x020b4248] = 0x00000000
ENET2_IEEE_T_FRAME_OK[0x020b424c] = 0x0000010b
ENET2_IEEE_T_1COL[0x020b4250] = 0x00000000
ENET2_IEEE_T_DROP[0x020b4254] = 0x00000000
ENET2_IEEE_T_DEF[0x020b4258] = 0x00000000
ENET2_IEEE_T_LCOL[0x020b425c] = 0x00000000
ENET2_IEEE_T_EXCOL[0x020b4260] = 0x00000000
ENET2_IEEE_T_MACERR[0x020b4264] = 0x00000000
ENET2_IEEE_T_CSERR[0x020b4268] = 0x00000000
ENET2_IEEE_T_SQE[0x020b426c] = 0x00000000
ENET2_IEEE_T_FDXFC[0x020b4270] = 0x00000000
ENET2_IEEE_T_OCTETS_OK[0x020b4274] = 0x0000dafa
ENET2_RMON_R_PACKETS[0x020b4284] = 0x00000004
ENET2_RMON_R_BC_PKT[0x020b4288] = 0x00000000
ENET2_RMON_R_MC_PKT[0x020b428c] = 0x00000000
ENET2_RMON_R_CRC_ALIGN[0x020b4290] = 0x00000001
ENET2_RMON_R_UNDERSIZE[0x020b4294] = 0x00000000
ENET2_RMON_R_OVERSIZE[0x020b4298] = 0x00000000
ENET2_RMON_R_FRAG[0x020b429c] = 0x00000003
ENET2_RMON_R_JAB[0x020b42a0] = 0x00000000
ENET2_RMON_R_RESVD_0[0x020b42a4] = 0x00000000
ENET2_RMON_R_P64[0x020b42a8] = 0x00000000
ENET2_RMON_R_P65TO127[0x020b42ac] = 0x00000000
ENET2_RMON_R_P128TO255[0x020b42b0] = 0x00000000
ENET2_RMON_R_P256TO511[0x020b42b4] = 0x00000001
ENET2_RMON_R_P512TO1023[0x020b42b8] = 0x00000000
ENET2_RMON_R_P1024TO2047[0x020b42bc] = 0x00000000
ENET2_RMON_R_P_GTE2048[0x020b42c0] = 0x00000000
ENET2_RMON_R_OCTETS[0x020b42c4] = 0x00000175
ENET2_IEEE_R_DROP[0x020b42c8] = 0x00000000
ENET2_IEEE_R_FRAME_OK[0x020b42cc] = 0x00000000
ENET2_IEEE_R_CRC[0x020b42d0] = 0x00000001
ENET2_IEEE_R_ALIGN[0x020b42d4] = 0x00000000
ENET2_IEEE_R_MACERR[0x020b42d8] = 0x00000000
ENET2_IEEE_R_FDXFC[0x020b42dc] = 0x00000000
ENET2_IEEE_R_OCTETS_OK[0x020b42e0] = 0x00000000
ENET2_ATCR[0x020b4400] = 0x00000031
ENET2_ATVR[0x020b4404] = 0x15942178
ENET2_ATOFF[0x020b4408] = 0x00000000
ENET2_ATPER[0x020b440c] = 0x80000000
ENET2_ATCOR[0x020b4410] = 0x00000000
ENET2_ATINC[0x020b4414] = 0x00000028
ENET2_ATSTMP[0x020b4418] = 0x00000000
ENET2_TGSR[0x020b4604] = 0x00000000
ENET2_TCSR0[0x020b4608] = 0x00000000
ENET2_TCCR0[0x020b460c] = 0x00000000
ENET2_TCSR1[0x020b4610] = 0x00000000
ENET2_TCCR1[0x020b4614] = 0x00000000
ENET2_TCSR2[0x020b4618] = 0x00000000
ENET2_TCCR2[0x020b461c] = 0x00000000
ENET2_TCSR3[0x020b4620] = 0x00000000
ENET2_TCCR3[0x020b4624] = 0x00000000
IOMUXC_GPR_GPR0[0x020e4000] = 0x00000000
IOMUXC_GPR_GPR1[0x020e4004] = 0x0f424005
IOMUXC_GPR_GPR2[0x020e4008] = 0x00000000
IOMUXC_GPR_GPR3[0x020e400c] = 0x00000fff
IOMUXC_GPR_GPR4[0x020e4010] = 0x00000000
IOMUXC_GPR_GPR5[0x020e4014] = 0x00000000
IOMUXC_GPR_GPR9[0x020e4024] = 0x00000000
IOMUXC_GPR_GPR10[0x020e4028] = 0x00000007
IOMUXC_GPR_GPR14[0x020e4038] = 0x00000000
[0x20280e0] = 0x80302001
[0x20280e4] = 0x80302001
[0x20280e8] = 0x80302001
[0x20280ec] = 0x80302001
SW_MUX_CTL_PAD_ENET2_RX_EN [0x020e00ec] = 0x00000010
SW_PAD_CTL_PAD_ENET2_RX_EN [0x020e0378] = 0x0001a0a8
SW_MUX_CTL_PAD_ENET2_RX_ER [0x020e0100] = 0x00000010
SW_PAD_CTL_PAD_ENET2_RX_ER [0x020e038c] = 0x0001a0a8
SW_MUX_CTL_PAD_ENET2_RX_DATA0 [0x020e00e4] = 0x00000010
SW_PAD_CTL_PAD_ENET2_RX_DATA0 [0x020e0370] = 0x0001a0a8
SW_MUX_CTL_PAD_ENET2_RX_DATA1 [0x020e00e8] = 0x00000010
SW_PAD_CTL_PAD_ENET2_RX_DATA1 [0x020e0374] = 0x0001a0a8
SW_MUX_CTL_PAD_UART3_TX_DATA [0x020e00a4] = 0x00000011
SW_PAD_CTL_PAD_UART3_TX_DATA [0x020e0330] = 0x0001a0a8
SW_MUX_CTL_PAD_UART3_RX_DATA [0x020e00a8] = 0x00000011
SW_PAD_CTL_PAD_UART3_RX_DATA [0x020e0334] = 0x0001a0a8
SW_MUX_CTL_PAD_UART3_CTS_B [0x020e00ac] = 0x00000011
SW_PAD_CTL_PAD_UART3_CTS_B [0x020e0338] = 0x0001a0a8

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fbrozovic
Contributor I

Hi Yvan,

did you get any closer to solving this problem? We have the same issue on a custom i.MX6ULL board with a LAN8720A PHY connected via RMII. TX works fine (i.e. ARP requests from U-Boot are sent out), but the MAC acts as if nothing at all is coming back from the PHY, even though data is present on RXD[0:1] (RX_ER and RX_EN look good as well).

384 Views
claudio1
Contributor II

Hi @Filip Brozovic

Have you get any step further?

I have exactly the same problem with my i.mx6ULL board.

I can send but the mac dont receive anything.

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