iMX6 Low Drop Out (LDO) Voltage

[MihaiNeagu]

We are using i.MX6 in our project.

Currently there is an internal discussion on the correct configuration of Low Drop Out (LDO) voltages.

We use QNX board start-up functions to configure LDO.

From the i.MX6 reference manual we understand that the configuration is done via configuring of Digital Regulator Core Register PMU_REG_CORE.

Current read value of the register is via command in32 0x020c8140 : 0x00502c12.

That is,  target voltage for VPU/GPU domain is 1.25V and for SOC is 1.2V.

voltage IN is 1.38V.

Can you please clarify whether this would be an acceptable setting.

If not, can you please let us know what are the risks with the current setting?

Also we see that a SW update is not always resulting in a corresponding register update( as seen  on read-out). That is, for some voltage steps, the SW is not able to set the register to the values as defined in SW.

Is this a known behavior on your side?

It would be helpful if you can share additional information in this regard.

Thank you!

[art]

Q1. Can you please clarify whether this would be an acceptable setting.

A1. With the PMU_REG_CORE register setting of 0x00502c12, the internal digital domain LDO regulator settings will be as follows.

1. The ARM Core supply voltage will be at 1.15V, that is acceptable for the ARM core operation at the clock frequencies of up to 792MHz.

2. The VPU/GPU supply voltage will be at 1.25V, that is acceptable for the operation at the clock frequencies of up to 352MHz.

3. The digital SoC supply voltage will be at 1.20V, that is acceptable for the operation at the whole SoC clock frequency range as well.

Q2. Is this a known behavior on your side?

A2. No, this is not a known behaviour. It may be related with too fast readback, since the PMU logic gets its clock from 24MHz source, and there might be no time for the register to be updated between write and too fast read back operation.

Have a great day,
Artur

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