Hello,
We're using i.mx8dxl and the reference manual says that lpspi only supports two native chip select lines per bus. We have a use case where we need 3 chip select lines on the same bus. ( No, it is not possible for our hardware team to route 2 chip select lines on one spi bus and another chip select line on another spi bus).
We've read that it is possible to use gpio as a chip select line. Are there any disadvantages of using the two native lines along with one gpio chip select line on the same bus? Will I need to run the clock at a lower rate because one of the chip select lines is a gpio?
Do you have an example for how to configure an lpspi with 2 native chip select lines and 1 gpio chip select line?
