i.MX8MP OCOTP SET/CLR Aliases Wrong in MIMX8ML_cm7.h Header?

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i.MX8MP OCOTP SET/CLR Aliases Wrong in MIMX8ML_cm7.h Header?

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scottNureva
Contributor II

Hello,

I ported the `fsl_ocotp` code from i.MXRT1170 SDK to program manufacturing fuses from the CM7.

Got the registers from the driver mapped to the ones provided by MIMX8ML8_cm7.h, but noticed that the SET/CLR macros are defined incorrectly.  This is in the latest SDK I pulled and also exists in the header provided in IAR.

I'm concerned because the fsl_ocotp driver makes use of a combination of direct register as well as the SET/CLR aliases--I could change the driver to remove all the SET/CLR references I suppose but want to double check I'm not missing anything...

Here's the CTRL register:

scottNureva_0-1714406029433.png


The direct ADDR/BUSY/ERROR masks (as expected) in the header:

scottNureva_1-1714406092212.png


The "SET/CLR/TOG" masks:

scottNureva_2-1714406143374.png

 

Here, the address mask is missing the top bit (0x1FF range rather than 0xFF) and the BUSY/ERROR/etc. bits are shifted to the right by one bit from where they should be...

Luckily, the OCOTP_CheckBusyStatus uses the correct mask and pulls from the register directly (no aliases)

scottNureva_3-1714406289748.png


Also, the OCOTP_CheckErrorStatus does the same...

However, OCOTP_ClearErrorStatus uses the CLR alias and the CLR_ERROR_MASK:

scottNureva_4-1714406411145.pngscottNureva_5-1714406435527.png


Which, when compared to the register, is really the BUSY location!

I'll likely hunt for all the SET/CLR/TOG options and replace with the full access values and masks...

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AldoG
NXP TechSupport
NXP TechSupport

Hello,

We do not support this kind of use case, for fuse operation we support using Cortex-A through uboot.

Best regards/Saludos,
Aldo.

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