Hi
I'm designing the PCB with i.MX8M Plus according to
"i.MX 8M Plus Hardware Developer's Guide, Rev.0, 03/2021".
I cannot meet the following two recommendations at the same time.
(A). On Page 22, it is recommended that "11. In general, the 200-ball LPDDR4 package should be placed 200 mils from the i.MX 8M Plus
(B). In Table 20, it is recommended that "CA3, CA2, CA1, CA0 match within 2ps.
In my present design, (A) is OK, but (B) is NG.
CA3, CA2, CA1, CA0 matches only within 48ps.
On the other hand, CA3, CA2, CA1, CA0 can match within CK_t +- 50ps.
Do I have to consider (B)?
If (B) is mandatory, Can I igone (A)?
If I ignore (A) and place LPDDR4 300mils from the SoC, I expect to be able to consider (B).
Thank you for your reply.
