i.MX6 DDR3 write leveling for T topology

[sugiyamatoshihi]

Hi, 

I read below thread.

https://community.nxp.com/message/810441?commentID=810441#comment-810441 

Then I don't think Write leveling calibration need for T topology. However, it should set something right value in  MMDC_MPWLDECTRLx. SABRESD board use fixed value 0x001F001F.  

How does this value chose? 

Can this value 1F use as standard for custom board?

Best Regards,

Sugiyama

[sugiyamatoshihi]

Hi, Jan,

Thank you for answer. I understood, but regarding to JEDEC JESD79-3F, Write leveling setup time like below.

If DDR3-1600 used, min setup time is 165pS. So, DQS should be 165pS faster than  CLK?

Is my understanding is correct?

If  this setup timing is  within 165nS, should DQS  be delayed a half clock by setting WL_HC_DEL?

Best Regards,

Sugiyama

[sugiyamatoshihi]

Hi, Jan,

I'm sorry I mistake unit. It is 165pS.

So, another word, How much DQ offset delay is applied to adjust to keep setup/hold timing before WL start? 

Best Regards,

Sugiyama

[jan_spurek]

Hello Sugiyama,

write leveling mode is not a normal operation mode and is used only for calibration. Therefore, it makes no sense to ensure the specified timings by layout - if it was the case, there would be a note in our hardware design guides. The controller takes care of this automatically based on the information provided from the Script Aid spreadsheet.

Best Regards,

Jan

[sugiyamatoshihi]

Hi, Jan,

Thank you for answer.

I understood t, but there is a write leveling error was set in WL_HW_ERR2. I red reference manual  and it describe about error as  If no transition is found then the MMDC indicates an error at MPWLGCR[HW_WL_ERR#.

I wonder why this error bit set because  there is high level in waveform.  I'd like to find the cause of this error.

Your advice is appreciated.

Bets Regards,

Sugiyama

[sugiyamatoshihi · Accepted solution]

Hi,

Regarding to Write leveling calibration, you should refer to below link.

Write Leveling register WL_SW_RESx 

Best Regards,

Sugiyama 

[sugiyamatoshihi]

Hi, Jan,

Do you have any information?

Best Regards,

Sugiyama

[sugiyamatoshihi]

Hi, Jan,

Thank you for answer.

There are questions.

If CLK and DQS rising edge is the same timing or DQS is slower, CLK logic level is 1 at the start of  write leveling test. There is no transition of 0->1 at the beginning. At this condition of no transition found , does write leveling test work correctly? 

Does it means DQS should be faster than CLK?

According to Table 3-3. DDR3 routing by byte group of Hardware Development Guide IMX6DQ6SDLHDG Rev. 2, DQS min length didn't specify. Does it means DQS should be faster than CLK and DQS length should be shorter than CLK length, instead of the same length in Table 3-2. DDR3 routing by the same length (continued)?

Best Regards,

Sugiyama

[jan_spurek]

Hello Sugiyama,

write leveling can only compensate for early DQS signals. Therefore, propagation time of DQS always has to be the same or shorter than CLK (i.e. faster).

Best Regards,

Jan

[sugiyamatoshihi]

Hi, Jan,

Yes, Stress test was passed with  that value.

I attached aid spread sheet,  initialization script, Calibration log and screen shot, Stress test log and screen shot.

In calibration log, Write DQS delay for DQS2 and DQS3 are 0/256 CK and MMDC_MPWLDECTRL1 =0x00000000.

What do you think?

DDR Freq: 528 MHz

ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x0004000D
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x00000000
Write DQS delay result:
Write DQS0 delay: 13/256 CK
Write DQS1 delay: 4/256 CK
Write DQS2 delay: 0/256 CK
Write DQS3 delay: 0/256 CK

Then I found below description in AN4467_DDR Calibration.pdf

11.1 Calibrating Write Leveling with a Preset Delay Value

• The write leveling delay parameters can be set without running the calibration sequence, by programming a preset value of absolute delay. The source of the preset value can be a write leveling calibration sequence done in the past. Alternately, the delay values can be a manual estimation of data delays based on DDR board route lengths. The following empirical rule, based on simulations and board experience, can be used: Each ([SDCLK_LENGTH] -[DQS_LENGTH])/6, measured in inches, implies 1 ns of delay. The time delay received by this rule should be converted to ddr_cycle/256 units, converted to hexadecimal, and applied to a delay register. Calibrating with a preset value is done by the following:
• Write the write leveling preset value to MMDC0_MPWLDECTRL0, MMDC0_MPWLDECTRL1, MMDC1_MPWLDECTRL0, and MMDC1_MPWLDECTRL1 registers.
• Set MMDC0_MPMUR[FRC_MSR], and MMDC1_MPMUR[FRC_MSR] bits.

I calculated based on this to get fix value.

SDCLK pattern length is 49.7mm and DQS2 length is 38.7mm, and difference is 11.0mm.

• ([SDCLK_LENGTH] -[DQS_LENGTH])/6, measured in inches, implies 1 ns of delay

   $DQS2

   PCB Pattern length 49.7-38.7=11mm= 0.43307inch,

   Pattern Delay　　　　(0.43307/6)*1nS=0.072178nS

   ddr_cycle/256 units

  Clock Delay at 528MHz       1/528=1.894nS

   One delay time=1.849/256=0.0073982nS

   Delay value for register      0.072178/0.0073982=9.756=~10, ->0xA

Is it possible to use this value for product?

Best Regards,

Sugiyama

[jan_spurek]

Hello Sugiyama,

I went through your Script Aid and Initialization Script and found nothing wrong with it. Before you run the calibration, you should also fill the MR1 value field because this register cannot be read from the memory chip and its contents change during calibration. This field then serves as a record to be used to reinstate the MR1 register.

The calculated value can be used but it is only an estimate. Your board may have a different stackup, different material with a different dielectric constant, different ratio between trace types (stripline vs. microstripline). All this results in different guided wavelengths of the signals and therefore, different delays. In adition, it does not account for parasitics introduced by internal chip structures and their parameters. To cover this in a calculation a very complex model would be required. The calibration compensates for all the mentioned phenomena and therefore it is the best way to go with.

As you don't have SDCLK and DQS traces length matched (in the T topology they should be), you need to provide values to the write leveling registers to compensate for the skew between the signals. Either obtained by the calibration or by calculation.

If your system is proven to be stable with the calculated values across some significant sample of boards there is no problem to use these values and you don't need to run the write leveling calibration.

Best Regards,

Jan

[sugiyamatoshihi]

Hi, Yan,

Thank you for review calibration results.

I asked customer to evaluate significant samples.

By the way, do you know why DDR stress test din't fail with write leveling delay with 0 value, but customer case fail boot?

I think delay=0 means clock and DQS timing is the same timing and no skew. It is ideal timing. Is it right?

Best Regards,

Sugiyama

[jan_spurek]

Hello Sugiyama,

By the way, do you know why DDR stress test din't fail with write leveling delay with 0 value, but customer case fail boot?

DDR Stress Test does not run Linux on i.MX, just tests the DRAM. Therefore the chip is not working in the same way as when it is running Linux - other peripherals are not utilized together with DDR, not that much additional interference from other data transfers is generated etc. So the 0 value can work in these conditions but if it is an edge value with little or no margin, the system can fail in normal conditions when it is subject to more interference.

I think delay=0 means clock and DQS timing is the same timing and no skew. It is ideal timing. Is it right?

Yes.

Best Regards,

Jan

[jan_spurek]

Hello Toshihisa,

write leveling calibration is used for delay compensation between CLK and DQS singals caused by length mismatch of the traces, which is natural for the fly-by topology. When using the T topology, the lengths should be ideally the same so the delay will be close to zero.

So MMDC_MPWLDECTRLx = 0x00000000 is a value to start with. However I still recommend to run the calibration as it compensates for all parasitics introduced to the system.

Best Regards,

Jan

[sugiyamatoshihi]

Hi, Jan,

Thank you for answer.

When write leveling calibration done by DDR calibration tool, the result of byte2 value is 0. Then 0 is applied to register, system didn't boot. However, if set 1F instead , it successfully boot.

So, calibration result seems wrong.

Then I'd like to I ask if fixed value 1F can be used for most system.

Best Regards,

Sugiyama

[jan_spurek]

Hello Sugiyama,

Does the DDR Stress Test pass with the calibrated values?

Could you please share the calibration log, initialization script, Script aid spreadsheet and screenshot of the DDR Test Tool with the settings applied to run the Calibration?

To my knowledge there is no generic value recommended for most systems - only that 1F value is usually better than default 0x00000000. It goes against the purpose of the calibration to issue such recommendations as each board design is different.

Best Regards,

Jan