Hi All,
In my application, I need to switch the MX50 boot mode from SD1 to USB-HID by software reset. As an experiment, I add the following code segment in u-boot to reset i.MX50 by internal watchdog. After making this change, the i.MX508 board can reset itself automatically after printing the SCR_SMBR register value.
====================================
unsigned short U16;
unsigned int U32;
U32 = readl(0x53FD0004);
printf("SBMR: %08x\n", U32);
udelay(3000000);
// disable warm reset
U32 = readl(0x53FD0000);
U32&= 0xFFFFFFFE;
writel(U32, 0x53FD0000);
// assert internal wdog_rst
U16 = readw(0x53F98000);
U16 &= 0xFFEF;
writew(U16, 0x53F98000);
====================================
If I set the boot configuration switches to USB-HID during u-boot, I found that the board will still boot from SD1. The SCR_SMBR register value is always 0x10000048 regardless to the configuration of boot switches.
However, if I press the reset button on the MX508 RD3 board, it boot into USB-HID immediately. I think it is due to the difference between power on reset and software reset. Anyone can help?
This solution works! Many thanks : )
Qiang Li said:
Hi Peter,
For your case, before enable the watch dog reset, you can write data 0x13000000 to LP General Purpose Register (SRTC_LPGR). Then after watch dog reset happen, the IMX50 ROM will check this register, if bit 28 of SRTC_LPGR is 1, the value in bit 25~0 will be loaded into SRC_SBMR, with the 0x13000000 in SRTC_LPGR, after watch dog reset, my iMX50 board will boot into download HID mode successfuly. (Bit 25~24 is the boot mode in SRC_SBMR)
You don't need modify the external boot pin setting, and WARM_RESET bit was also not be changed. Of cource, for normal case, you need clear the bit 28 of SRTC_LPGR, other wize, all watch dog reset will run into download mode.
By the way, after you set 0x13000000 to SRTC_LPGR, it needs some delay to be active, you'd better to read back it to double confirm the value had been updated in SRTC_LPGR, then generate the watch dog reset.
Please try it.
Hi Peter,
For your case, before enable the watch dog reset, you can write data 0x13000000 to LP General Purpose Register (SRTC_LPGR). Then after watch dog reset happen, the IMX50 ROM will check this register, if bit 28 of SRTC_LPGR is 1, the value in bit 25~0 will be loaded into SRC_SBMR, with the 0x13000000 in SRTC_LPGR, after watch dog reset, my iMX50 board will boot into download HID mode successfuly. (Bit 25~24 is the boot mode in SRC_SBMR)
You don't need modify the external boot pin setting, and WARM_RESET bit was also not be changed. Of cource, for normal case, you need clear the bit 28 of SRTC_LPGR, other wize, all watch dog reset will run into download mode.
By the way, after you set 0x13000000 to SRTC_LPGR, it needs some delay to be active, you'd better to read back it to double confirm the value had been updated in SRTC_LPGR, then generate the watch dog reset.
Please try it.
Peter Chan said:
I also attempt to change the watchdog reset to cold reset by clear the WARM_RESET_ENABLE bit in SRC_SCR register. However, it still does not work.
I also attempt to change the watchdog reset to cold reset by clear the WARM_RESET_ENABLE bit in SRC_SCR register. However, it still does not work.
Only for power on reset and cold reset, the IIM will be updated. You can reference to iMX50 reference manual, "49.3.1.2.2.1 IPP_RESET_B(POR)", "49.3.1.2.2.2 COLD RESET" and "49.3.1.2.2.3 WARM RESET" to find the difference for reset.