I am using the FlexSPI interface in an i.MX 8M Nano processor to communicate with a FPGA in SDR mode. The FPGA outputs data on the falling edge of SCLK and outputs a read strobe whose rising edge is aligned to the rising edge of SCLK, i.e. centred on the data.
In the i.MX 8M Nano Applications Processor Reference Manual (Rev 2, 07/2022), section 10.2.4.14.3 states that in this case the FlexSPI controller should sample the read data with the read strobe directly (DLL bypassed). In the i.MX 8M Nano Applications Processor Datasheet (Rev 5, 09/2022) this is contradicted - figure 39 in section 3.9.9.1.2 shows that data is sampled on the falling edge of the internal read strobe which is generated by delaying the external DQS by half a clock cycle. However, as can be seen in figure 39, this would mean that the FlexSPI controller would only start sampling on the second data item.
From hardware testing, it does appear that the FlexSPI controller samples data on the falling edge of the read strobe, which is incorrect behaviour for SPI mode 0.
Can someone confirm this is the actual behaviour of the FlexSPI controller (and that the reference manual is therefore incorrect).
By the way, figures 37 to 39 in the consumer products version of the datasheet are completely wrong. Fortunately the correct figures appear in the industrial products version.
