i.MX 6UltraLite power down counter event behavior

[mborjess]

Hi.

We are developing a platform centered around an i.MX 6UltraLite but are struggling to understand the details regarding the power-down counter event. The reference manual states:

The power-down counter inside WDOG will be enabled out of reset. This counter has a fixed timeout value of 16 seconds, after which it will drive the WDOG_B signal low.

It goes on to say that we can prevent this behavior by clearing the PDE bit. We wanted to verify this behavior and removed all writes to the WDOG1 registers in our bootloader (u-boot). We then ran the "panic" command on the u-boot command line, dumping the WDOG1 registers and sending the CPU into an infinite loop.

Modified hang() function, where we end up after calling "panic":

/**
 * hang - stop processing by staying in an endless loop
 *
 * The purpose of this function is to stop further execution of code cause
 * something went completely wrong.  To catch this and give some feedback to
 * the user one needs to catch the bootstage_error (see show_boot_progress())
 * in the board code.
 */
void hang(void)
{
#if !defined(CONFIG_SPL_BUILD) || \
        (CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) && \
         CONFIG_IS_ENABLED(SERIAL))
    puts("### ERROR ### Please RESET the board ###\n");
#endif
    struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
    printf("Watchdog 1 settings:\n");
    printf("    WCR=0x%04X\n", wdog1->wcr);
    printf("    WSR=0x%04X\n", wdog1->wsr);
    printf("    WRSR=0x%04X\n", wdog1->wrsr);
    printf("    WICR=0x%04X\n", wdog1->wicr);
    printf("    WCMR=0x%04X\n", wdog1->wmcr);

    bootstage_error(BOOTSTAGE_ID_NEED_RESET);
    if (IS_ENABLED(CONFIG_SANDBOX))
        os_exit(1);
    for (;;)
        ;
}

Last snippet of the log, where the register values are dumped:

=> panic

resetting ...
### ERROR ### Please RESET the board ###
Watchdog 1 settings:
    WCR=0x0030
    WSR=0x0000
    WRSR=0x0010
    WICR=0x0004
    WCMR=0x0001

The printed register values indicate the the PDE bit is still set, so we expect that the CPU should be reset by the watchdog (power-down counter) at some point after doing this. Unfortunately, that doesn't happen. Are there any other parts of the power-down reset mechanism we are missing?

[mborjess]

Thank you for the reply. I think my main point of confusion is the relation between WDOG_B and watchdog reset, are they synonymous? I noticed that the WDOG_B signal can be routed to external pins, does that mean that we would need to have an external reset logic to take benefit of the power-down counter reset?

[JorgeCas]

Hello, I hope you are doing well.

If PDE is 1 and are presented the scenarios of section 57.5.6.2 WDOG_B generation (specifically WDOG power-down counter timeout) of reference manual it will drive the WDOG_B signal low.

Best regards.