i.MX 6SoloX - M4 PWM gets disturbed by Linux

[Kisle]

Hi all,

we are having some trouble with the imx6 PWM generated by the M4.

I want to generate a PWM. I tested different pins / PWM. For example via IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 (PWM1_OUT) and (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 (PWM2_OUT). With both pins I see the same problem:

It generates a clean 30% PWM with my desired Frequency. However, the signal gets "interrupted" and pulled to low at random intervalls.

The signal is definetly being disturbed by linux. If Linux is not booted everything looks still fine.

We checked the device tree and we cannot see any device occupying the same pins. We setup the shared clocks occordingly and we tried diffirent clock sources of the pwm.

Some code fragments for better understanding:

CCM_SetRootMux(CCM, ccmRootPerclkClkSel, ccmRootmuxPerclkClkIpgClkRoot);

RDC_SetPdapAccess(RDC, rdcPdapPwm1, 3 << (BOARD_DOMAIN_ID * 2), false, false);
CCM_ControlSharedGate(CCM, ccmCcgrGatePwm1Clk, ccmClockNeededAll, SHARED_CLK_PWM1);
CCM_ControlSharedGate(CCM, ccmCcgrGatePwm1Clk, ccmClockNeededAll, SHARED_CLK_IPG);
CCM_ControlSharedGate(CCM, ccmCcgrGatePwm1Clk, ccmClockNeededAll, SHARED_CLK_PERCLK);
set_iomux(MX6SX_PAD_GPIO1_IO10__PWM1_OUT, 0x30B0);

The device tree devices have the same ordering as the shared clock enums.

I am pretty sure that the pin setup and PWM itself is fine. Since the PWM signal is exactly how we expect it do be, it just gets "interrupted" by Linux. Maybe linux somehow uses the clock or overwrites the pin configs?

[Kisle · Accepted solution]

Hi.

I got this one sorted out. Setting the following bits in the PWM solved this issue:

PWM_PWMCR_REG(pBase) |= (((uint32_t)(((uint32_t)(1))<<PWM_PWMCR_DOZEN_SHIFT))&PWM_PWMCR_DOZEN_MASK);
PWM_PWMCR_REG(pBase) |= (((uint32_t)(((uint32_t)(1))<<PWM_PWMCR_STOPEN_SHIFT))&PWM_PWMCR_STOPEN_MASK);
PWM_PWMCR_REG(pBase) |= (((uint32_t)(((uint32_t)(1))<<PWM_PWMCR_WAITEN_SHIFT))&PWM_PWMCR_WAITEN_MASK);
PWM_PWMCR_REG(pBase) |= (((uint32_t)(((uint32_t)(1))<<PWM_PWMCR_DBGEN_SHIFT))&PWM_PWMCR_DBGEN_MASK);

[Kisle]

There is some mix up in my initial comment and I cant seem to edit.
of course when Testing with PWM1_OUT i was using GPIO1_IO10_PWM1_OUT
and when testing with PWM2_OUT using GPIO1_IO11_PWM2_OUT and the proper according CCM settings.

Both pins show the exact same behavior.