chip bug of fractional part of DI Base Sync Clock Gen 0 Register

[jiadawang]

Hi,

I am working on i.MX6 platform, I found the use of fractional part of DI Base Sync Clock Gen 0 Register (IPUx_DIx_BS_CLKGEN0)

is not always a good idea. I am using external PLL clock to drive clk_di_pixel clock to generate proper clock rate for HDMI display,

but when use fractional part of CLKGEN0, clock will be unstable and the PLL is not working properly, or rather doesn't work at all.

This makes me believe there probably is a chip bug with fractional part of DI Base Sync Clock Gen 0 register.

Bug I can't find any information about this in i.MX6 user reference manual,

Could anyone in Freescale help me to clarify on this?

Thanks,

jiada

[Yuri]

Pixel IPU clock for Display has high jitter and does not have 50% duty cycle.

This is expected behavior, when the clock divider is set to a value that is not

an integer.

When the divider is set to a non-integer value, the average frequency of the

clock will be correct, but the clock will jitter.

[jiadawang]

Hi YuriMuhin_ng

Thanks for the answer,

as you have mentioned, when fractional part of divider is used, the clock will jitter.

that means it can't be used to drive external display, when they are not so forgiving to the pixel clock?

Is there anything we could do in driver to make pixel clock stable, even we are using fractional part?

As I have observed, set fractional part to 0x8 (0.5) seems works fine,  do you have any idea about this?

Thanks,

Jiada

[Yuri · Accepted solution]

Please look at my comments below :

1.

> ... that means it can't be used to drive external display, when they are not so forgiving to the pixel clock?

Correct.

Perhaps it makes sense to apply external clock source in such case.

2.

> Is there anything we could do in driver to make pixel clock stable, even we are using fractional part?

Hardly :-(

Just as a rough example : if fractional part is 0.3, clock will have duty cycle 2:1 and we cannot change

it in software.

3.
>As I have observed, set fractional part to 0x8 (0.5) seems works fine,  do you have any idea about this?

It depends on display specs regarding clocks.

[jiadawang]

Hi YuriMuhin_ng

Thanks for your answer,

have you did any test for 0x8 (0.5), what's the clock duty cycle, when fractional part is to set 0x8?

[Yuri]

> ... have you did any test for 0x8 (0.5) ... ?

As for me - no.