are the DDR3 calibrations supported by u-boot for iMX6 ?

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are the DDR3 calibrations supported by u-boot for iMX6 ?

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abraham_v
Contributor IV

From DDR3 documentation, I understand that there are 4 types of calibrations that can be done. Namely,

  • ZQ calibration
  • Read calibration
  • Write Leveling
  • Write calibration

Are these supported in the uboot code for iMX6 ? I haven't found any mention of them for the iMX6Q sabresd reference board.

We are designing a new board based on the iMX6D processor using two DDR3 chips from Nanya on a 32-bit bus totally 1GB of RAM. We have used daisy chain topology for our new board and we feel that we may need these calibrations during bringup. Do you have any idea how we can do these?

-Abraham V.

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AnsonHuang
NXP Employee
NXP Employee

Hi, Abraham

     The DCD table has done all the calibration you mentioned, see below from flash_header.S, you can get them from MMDC chapter of RM.

/* HW ZQ */

328 MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003)

329

/* Write leveling */

330 MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)

331 MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)

332 MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)

333 MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)

334

335 MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x4333033F)

336 MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x032C031D)

337 MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83c, 0x43200332)

338 MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x031A026A)

/* Read calibration */

339 MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x4D464746)

340 MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x47453F4D)

/* Write calibration */

341 MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x3E434440)

342 MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x47384839)

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kwang
Contributor II

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AnsonHuang
NXP Employee
NXP Employee

Hi, Abraham

     The DCD table has done all the calibration you mentioned, see below from flash_header.S, you can get them from MMDC chapter of RM.

/* HW ZQ */

328 MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003)

329

/* Write leveling */

330 MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)

331 MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)

332 MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)

333 MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)

334

335 MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x4333033F)

336 MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x032C031D)

337 MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83c, 0x43200332)

338 MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x031A026A)

/* Read calibration */

339 MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x4D464746)

340 MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x47453F4D)

/* Write calibration */

341 MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x3E434440)

342 MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x47384839)

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kwang
Contributor II

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abraham_v
Contributor IV

AnsonHuang,

Thank you. Looks like that was what I needed.

I have a supplementary question involving some of those registers. If we look in the iMX6 reference manual the four registers,

MMDC Core ODT Timing Control Register (MMDCx_MDOTC)

MMDC Core Timing Configuration Register 0 (MMDCx_MDCFG0)

MMDC Core Timing Configuration Register 1 (MMDCx_MDCFG1)

MMDC Core Timing Configuration Register 2 (MMDCx_MDCFG2)

define timing parameters for DDR3. It's specified in terms of clocks. (eg: MMDCx_MDCFG0: tRFC bits31-24 can be configured as either 1 clock, 2 clock, ... 256 clocks). Is this referring to the external clock on DDR bus or some internal MMDC clock?

-Abraham V.

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AnsonHuang
NXP Employee
NXP Employee

Hi, Abraham

     This is referring to the external clock of DDR BUS, such as on i.MX6Q, it is 528M.

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abraham_v
Contributor IV

Thanks!

-Abraham V.

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AnsonHuang
NXP Employee
NXP Employee

HI, Abraham

        You may check the flash_header.S, the DDR3 calibration should be done in DCD table.

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