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What is the procedure to control brightness of led using PWM on imx8mp-evk?

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What is the procedure to control brightness of led using PWM on imx8mp-evk?

‎04-07-2024 11:42 PM
281 Views
vrutik7781
Contributor I

Hi,
On my imx8mplus evk i am trying to enable PWM for controlling LEDs,
What is the procedure to the PWM imx8mp-evk? Is there any step-by-step guide available?
this is what I have in my imx8mp-evk-root.dts:

pwm1grp {
fsl,pins = <0x18 0x278 0x00 0x01 0x00 0x116>;
phandle = <0x1f>;
};

pwm2grp {
fsl,pins = <0x40 0x2a0 0x00 0x02 0x00 0x116>;
phandle = <0x20>;
};

pwm4grp {
fsl,pins = <0x12c 0x38c 0x00 0x02 0x00 0x116>;
phandle = <0x21>;
};

bus@30400000 {
compatible = "fsl,aips-bus\0simple-bus";
reg = <0x30400000 0x400000>;
#address-cells = <0x01>;
#size-cells = <0x01>;
ranges;
phandle = <0xd9>;

pwm@30660000 {
compatible = "fsl,imx8mp-pwm\0fsl,imx27-pwm";
reg = <0x30660000 0x10000>;
interrupts = <0x00 0x51 0x04>;
clocks = <0x02 0xdc 0x02 0xdc>;
clock-names = "ipg\0per";
#pwm-cells = <0x03>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x1f>;
phandle = <0xda>;
};

pwm@30670000 {
compatible = "fsl,imx8mp-pwm\0fsl,imx27-pwm";
reg = <0x30670000 0x10000>;
interrupts = <0x00 0x52 0x04>;
clocks = <0x02 0xdd 0x02 0xdd>;
clock-names = "ipg\0per";
#pwm-cells = <0x03>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x20>;
phandle = <0xb3>;
};

pwm@30680000 {
compatible = "fsl,imx8mp-pwm\0fsl,imx27-pwm";
reg = <0x30680000 0x10000>;
interrupts = <0x00 0x53 0x04>;
clocks = <0x02 0xde 0x02 0xde>;
clock-names = "ipg\0per";
#pwm-cells = <0x03>;
status = "disabled";
phandle = <0xdb>;
};

pwm@30690000 {
compatible = "fsl,imx8mp-pwm\0fsl,imx27-pwm";
reg = <0x30690000 0x10000>;
interrupts = <0x00 0x54 0x04>;
clocks = <0x02 0xdf 0x02 0xdf>;
clock-names = "ipg\0per";
#pwm-cells = <0x03>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x21>;
phandle = <0xdc>;
};

lvds_backlight {
compatible = "pwm-backlight";
pwms = <0xb3 0x00 0x186a0 0x00>;
status = "okay";
brightness-levels = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64>;
default-brightness-level = <0x50>;
phandle = <0x13b>;
};

pinctrl_pwm1 = "/soc@0/bus@30000000/pinctrl@30330000/pwm1grp";
pinctrl_pwm2 = "/soc@0/bus@30000000/pinctrl@30330000/pwm2grp";
pinctrl_pwm4 = "/soc@0/bus@30000000/pinctrl@30330000/pwm4grp";


pwm1 = "/soc@0/bus@30400000/pwm@30660000";
pwm2 = "/soc@0/bus@30400000/pwm@30670000";
pwm3 = "/soc@0/bus@30400000/pwm@30680000";
pwm4 = "/soc@0/bus@30400000/pwm@30690000";

Do i need to configure the pwm in my dts? is there another way i can enable it?

If not, how do i add it to my device tree?

j21 connector has 40 pins below are the pin details

vrutik7781_0-1712557896217.jpegvrutik7781_1-1712557906134.png

i am trying to use pwm4_3v3 which is 32 pin on j21 connector .

after running gpioinfo command on target machine in GPIOCHIP5 show 16 lines , in those 16 lines , PWM line is not present . whether i need pwm line to controll brightness of led .

vrutik7781_2-1712558135379.jpeg

please give answers to this questions
1.Do i need to configure the pwm in my dts? is there another way i can enable it?
   If not, how do i add it to my device tree?
2.Do i need any pwm line to control the brightness of led , what is procedure to control the brightness of led using pwm

 

 

imx8mp-evk-root.dts
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1 Reply

‎04-08-2024 07:53 AM
260 Views
Bio_TICFSL
NXP TechSupport
NXP TechSupport

Hello,

1. The PWM interfaces

The common {cpu-family} CPU device tree file contains entries for all the PWM channels:

{cpu-family} device tree
	pwm1: pwm@30660000 {
		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
		reg = <0x30660000 0x10000>;
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
			 <&clk IMX8MM_CLK_PWM1_ROOT>;
		clock-names = "ipg", "per";
		#pwm-cells = <2>;
		status = "disabled";
	};

	pwm2: pwm@30670000 {
		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
		reg = <0x30670000 0x10000>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
			 <&clk IMX8MM_CLK_PWM2_ROOT>;
		clock-names = "ipg", "per";
		#pwm-cells = <2>;
		status = "disabled";
	};

	pwm3: pwm@30680000 {
		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
		reg = <0x30680000 0x10000>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
			 <&clk IMX8MM_CLK_PWM3_ROOT>;
		clock-names = "ipg", "per";
		#pwm-cells = <2>;
		status = "disabled";
	};

	pwm4: pwm@30690000 {
		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
		reg = <0x30690000 0x10000>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
			 <&clk IMX8MM_CLK_PWM4_ROOT>;
		clock-names = "ipg", "per";
		#pwm-cells = <2>;
		status = "disabled";
	};

IOMUX configuration

You must configure the pads that are to be used as {cpu-family} PWMs.

  {cpu-family} pads should only have one IOMUX configuration. Remove other configurations for those pads, like GPIO, when configuring them as PWMs.

The default device tree enables PWM2 available on the ConnectCore 8M Mini Development Kit J46 expansion connector:

  • PWM2 corresponds to pad GPIO1_IO13

  • PWM3 corresponds to pad GPIO1_IO14 (disabled by default due to conflicts with USB-OTG2 power enable)

  • PWM4 corresponds to pad GPIO1_IO15 (disabled by default due to conflicts with USB-OTG2 overcurrent detect)

Depending on the frequency of the PWM signal and the hardware around it, you must carefully select the pad settings (the numerical values following the IOMUX definition on the device tree). See Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt for information about the different values. Also see the NXP application note AN5078 Influence of pin setting on system function and performance for additional information.

Using the PWM channels

Control PWM signal from sysfs

Each PWM interface is registered in the system as a standalone PWM controller.

The PWM interfaces appear under /sys/class/pwm:

ls /sys/class/pwm/
pwmchip0  pwmchip6

The PWM interfaces begin numbering with an index of 0. The indexes are calculated using the number of channels of the previous interface. On the example above:

  • MCA PWM0 chip 4 (6 channels) is pwmchip0

  • {cpu-family} PWM2 (1 channel) is pwmchip6

Each CPU PWM interface only manages one PWM signal. Check the number of channels of an interface by printing the value of npwm:

cat /sys/class/pwm/pwmchip6/npwm
1

To access one channel of a PWM interface, export the channel index (0 since there is only one):

echo 0 > /sys/class/pwm/pwmchip6/export
  You won’t be able to request PWM channels that are in use by other drivers, like those used by the backlight.

Now you can access the PWM channel and configure its settings:

ls /sys/class/pwm/pwmchip6/pwm0/
duty_cycle  enable      period      polarity    power       uevent

Period and duty cycle must be given in nanoseconds. For example, to configure a 100kHz signal with 20% duty cycle:

echo 10000 > /sys/class/pwm/pwmchip6/pwm0/period

echo 2000 > /sys/class/pwm/pwmchip6/pwm0/duty_cycle

To enable the PWM signal:

echo 1 > /sys/class/pwm/pwmchip6/pwm0/enable

The default polarity is normal (active high for the duty cycle). To invert the polarity:

echo inversed > /sys/class/pwm/pwmchip6/pwm0/polarity

 

Regards

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