We would like to utilize video overlay and encoding at the same time while keeping the video latency at minimum.
We started with mxc_v4l2_overlay unit test to display video overlay on HDMI connected display. We have modified the code to use 32bpp colors because RGB565 caused ugly banding on color gradients. We also moved color space conversion (YCbCr to RGB) from IC to DP to reduce latency even further. We are quite happy with overlay so far, but we need to add encoding to our application as well.
Currently we use only one DMA channel (IDMAC) moving data from IPU (camera is connected to CSI using 16bit parallel bus) directly into framebuffer. DP then gets data from framebuffer and do color space conversion from YCbCr to RGB on the fly, before sending data to HDMI output.
I can use mxc_vpu_test unit test to encode data from CSI into desired format (H.264 would be best for us). Unfortunately when I run encoding task using the unit test, the overlay gets somehow broken and does not work anymore. I think that there is some kind of collision between overlay task and encoding task, because both of them try to get data directly from CSI.
How can we modify encoding task in such way that it would either read data buffer that is already being used for display (framebuffer in system memory) or branch our flow using additional DMA channel to copy data to different buffers and use those for encoding?
I tried to find some information in reference manual (IMX6DLRM) which in fact mentions that there can be several video flow active at same time (for example for viewfinder and encoding) and also talks about "branching from VFx" for RCx (recording flow). Unfortunately I am unable to find further information on this topic, so I do not know how can we achieve that.
Hardware setup:
Software setup:
Thank you very much for any tips or hints in this matter.
Hello,
Please try using Gstreamer pipeline.
Use "i.MX_6_Series_Ubuntu_Multimedia_User's_Guide.pdf" of L3.0.35
for details.
Have a great day,
Yuri
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Dear Yuri,
thanks for the response. Unfortunately I am not able to find the document you are talking about on NXP's site. Could you please send me link where I can download it?
Best Regards
Ivo