Two RMII interface on i.MX6 Solo

[erichwolf]

Hi all,

we want to connect two external PHY (LAN8720A) on i.MX6 Solo (RMII interface).

Refer to

i.MX 6SoloX Applications Processor Reference Manual, Rev. 0, 2/2015

24.3 External Signals, the table describes the external signals of ENET1 and  ENET2.

I match the ENET1 signals:

ENET1_MDC                                 =             RMII_MDC

ENET1_MDIO                                =            RMII_MDIO

ENET1_RX_DATA0                       =            RMII_RX_DATA0

ENET1_RX_DATA1                       =            RMII_RX_DATA1

ENET1_TX_DATA0                       =            RMII_TX_DATA0

ENET1_TX_DATA1                       =            RMII_TX_DATA1

ENET1_RX_ER                            =            RMII_RX_ER

ENET1_RX_EN                           =             RMII_CRS_DV

ENET1_REF_CLK1                    =             RMII_25MHz_PHY_CLK

Is that correct?

Is the signal ENET1_REF_CLK1 in the right power domain?

Could I use the ENET1_REF_CLK1 to clock the PHY?

I found in the table a signal "ENET1_REF_CLK_25MHz",

but there is no Mode given (" - ").

Could you please let me know - what does it mean?

Regards

Erich

[erichwolf]

Hello Weidong,

thanks a lot, I will use ENET2_RX_CLK.

Regards

Erich

[weidong_sun · Accepted solution]

Hello Erich,

    See following, please !

-----PHY Clock : ENET2_RX_CLK pin can be multiplexed as ENET_REF_CLK_25M, which is for PHY Clock.

    The level is determined by the voltage of NVCC_ENET, on evk board, the level is 3.3V. you should check the phy's datasheet you are using, then decide if level shifter will be used.

that is : ENET2_RX_CLK pin --->ENET_REF_CLK_25M(3.3V)--->level shifter(if needed)--->PHY's clock input pin(XTLI)

Hope above suggestion can help you !

Regards,

Weidong