Timing for UARTx_USR2[TXDC]?

[kimbp]

According to the i.MX6 reference manuals UARTx_USR2[TXDC] goes high when TxFIFO and Shift Register is empty

My concern is that it is unclear whether parity (optional) and stop bit(s) are included in the term "Shift Register is empty"

If not I see no means to ensure all bits are transmitted before toggling UARTx_UCR2[CTS] while using it to control direction in RS485 mode.

Anyone who can confirm parity and stop bits are also covered by TXDC?

If not - are there other means to detect 'transmission fully complete'?

The lower a bit rate the higher risk of changing direction too soon and thus make an invalid 'last' character transmission

The reference manual deliberately say about UARTx_USR2[TXFE ] (in Transmitter FIFO empty Interrupt Suppression):

the interrupt flag is set when the last bit of the character has been transmitted, for example, before the transmission of the parity bit (if exists) and the stop bit(s).

But again - this is not TXDC

[Pavel · Accepted solution]

There is no activity after TXDC bit setting.

This bit usually is used if i.MX6 UART is RS485 transceiver.

Setting of the TXDC is used for switching the RS485 transmitter.

Have a great day,
Pavel Chubakov

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[kimbp]

So in order to really make this answer complete:

If making a timing diagram showing UARTx_USR2[TXDC] and the TX-line, there will still be line activity from stop bit(s) and parity bit at the TX-line after asserting TXDC?

[Pavel]

The UARTx_USR2[TXDC] goes high if TxFIFO and Shift Register is empty.

This bit is high if there are no bits in the i.MX6 UART shift register.

It means that all bits are sent and transmission fully complete.

Have a great day,
Pavel Chubakov

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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