SPI DMA Transfer Delay

[marcus-castlepeakinc]

Hello,

Does anyone know what causes the ~200ns clock delays between words in a dma spi transfer?

Does it have to do with the latency with of wait_for_completion_timeout for rx/tx in

spi_imx_dma_transfer?

Thanks!

[kef2]

This is caused by spi driver doing separate 8 bit transfers (ECSPIx_CONREG . BURST_LENGHT = instead of doing single transfer with BURST_LENGTH set to total transfer bit count. For the same reason hardware chip select is of no use, forcing nearly everyone to use software toggled CS.