S/PDIF Tx clk

[BartholomeusDias]

Hi,

I would like to change the clock source on which the S/PDIF transmitter operates, so it can be clocked by an external clock synthesizer. The reason for this is that I would like to synchronize the S/PDIF outputs of multiple individual devices.

Currently I see 2 options for this:

1. Set the clock source for audio PLL1&2 to the pad clock input on for example CLKIN1 or CLKIN2 and provide a 24MHz clock there from my synthesizer that I can slightly tune.

2. Use the EXT_CLK_2 or EXT_CLK_3 input to clock the S/PDIF block directly with a correct audio frequency like 24.576 or 22.579Mhz from the synthesizer.

Regarding option 1:

In the u-boot sources, clk_imx8mm.c, "decode_fracpll" I see that any clk source other than the 24Mhz SYS_XTAL is refused:

/* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
	if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0)
		return 0;

Is this because the hardware PAD inputs on the SOC are non-functional, or because the driver in it's current state has not (yet) been written to support these pins?

Regarding option 2:

It looks like I will have to severley re-write fsl_spdif.c to make this work.

Would you know of alternative routes I could take to make this work?

Thanks in advance!

[BartholomeusDias]

Ok, thanks for your feedback. I will try the EXT_CLK_2 first.

I have also seen there is a pin for SPDIF_EXT_CLK but from the reference manual it is unclear to me what this pin is used for and what the specs are.

Could you please elaborate on that?

[JorgeCas]

Hello,

That pin is used for external clock signal (EXT_CLK), the maximum input clock frequency is 66 MHz.

Best regards.

[JorgeCas]

Hello,

The first option it is difficult because that 24 MHz signal is for the whole system and it will cause issues on other modules. You should be able to get the external clock from your synthesizer on EXT_CLK_2 or EXT_CLK_3 configuring it on CCM.

Best regards.

[BartholomeusDias]

Dear Jorge7u7,

Thanks for your quick reply. For clarity I'm referring all things to a IMX8 Nano.

To fully understand the clocking system I have this follow up question.

My intention was to only assign CLKIN1 to the clock source of AUDIO_PLL1 and AUDIO_PLL2 by setting the PLL_REF_CLK_SEL and PAD_CLK_SEL bits of reg 3036_0000h and respectively 3036_0014h.

My assumption is that all other PLL's will still run from the 24MHz crystal.

In your reply, do you mean that if I want to assign CLKIN1 to these specific audio PLL's, I need to do that for all others too? If not, is your answer still applicable?

In any case I will investigate option 2 further as well.

Thanks!

[JorgeCas]

Hello,

Got it, your assumption is correct but, as you can see on iMX8M nano reference manual on Clock Control Module section, the AUDIO_PLL1 and AUDIO_PLL2 could be used on other modules and cause issues with the clock signal if you change the clock configuration.

Best regards.