Question about I.MX6 SDMA Interrupt Generation

[ahmedabdelhalee]

Dear All,

I have a technical question in Chapter 41 (SDMA) of I.MX6SL reference manual:

Shall the generated interrupt status due to the "Done 3" instruction be masked with INTRMASK register before triggerring the interrupt signal to the ARM platform or not?

Thanks in advance,

Ahmed

[Yuri]

   The SDMA has ability to "warn the ARM platform when an incoming DMA request was

detected and it triggers a channel that is already pending or being serviced." SDMAARM_EVTERR is used for it.

If such kind of events are needed to be served / tracked, it is required to unmask (enable) corresponding events

in SDMAARM_INTRMASK. Generally it is possible to mask (disable) some channles in the INTRMASK - in order
to skip possible overflow of data for some active channel. 

   "If any of the INTRMASK bits is set, the EVTERR register should also be scanned, or at least cleared, since CHNERR[i]

conditions generate interrupts which are indistinguishable from H[i] interrupts."

[_at]

Hi Yuri,

We have customized platform of SabreSD I.MX 6Q.
As you said, "" Generally it is possible to mask (disable) some channles in the INTRMASK - in order to skip possible overflow of data for some active channel. ""
Now, question regarding SDMAARM_INTRMASK register [Chapter 55 (SDMA), pg 4871, of I.MX6Q reference manual].
It state that:: "" The Interrupt Mask Register contains 32 interrupt generation mask bits. If bit HIMASK[i] is set, the HI[i] bit is set and an interrupt is sent to the ARM platform when a DMA request error is detected on channel i (for example, EVTERR[i] is set).""

On our platform, when i read this register values::
    /* Code start */
    stat = readl_relaxed(sdma->regs + SDMA_H_INTRMSK);
    // Code end  */
I got value always 'stat=0'.

But, even though there is no masking bit 'set', ARM Platform got interrupt & EVTERR[i] bit is set.
Reason to ask this, we are facing problem of Audio lost & only log we got that EVTERR[i] is set & "overflow of data" occurs for (i) DMA channels.

We have created discussion here: https://community.freescale.com/message/380162

Is SDMA disable/stop the DMA channel in case it found overflow of data for that channel?

Is there any way by which SDMA continue with its execution & don't stop the DMA Channel ?

Please reply us !!

-Ankit.

[Yuri]

"If part or whole data is not in the FIFO, an external burst read access is
performed to provide the missing data. The SDMA is stalled as long as the

required read data is not complete."

Regards,

Yuri.

[ahmedabdelhalee]

Thank you Yuri for your response about channel overflow condition, but I wanted also to know whether the masking through "SDMA_INTRMASK" register affects the generated interrupt via execution of "Done 3" instruction or once the "Done 3" instruction is decoded by SDMA, an interrupt is generated to the ARM platform regardless of the "SDMA_INTRMASK" register value (assuming no overflow in this case)?

Best Regards,

Ahmed

[Yuri]

For "done 3" an interrupt is generated to the ARM platform regardless of the "SDMA_INTRMASK".

[ahmedabdelhalee]

Thank you :smileyhappy:..  this definitely answers my question.

Best Regards,

Ahmed