PID interrupt for eDMA on i.MX RT1170

[wlan]

I'm writing a driver for an AD7091 ADC chip with which I communicate over SPI. I'm using eDMA to trigger the SPI transfers (eDMA in Periodic Trigger Mode, see below) because we're doing a lot of conversions in a short time.

The AD7091 requires a low pulse on its CONVST line to trigger a conversion before the ADC conversion result can be read so in the PID's interrupt handler I added a function to toggle the CONVST.

Sounds simple enough. The problem is that on some occasions, the PID interrupt handler is executed AFTER the start of the SPI transfer which it triggers and I cannot find out why. It seems there is a race condition between the interrupt handler and triggering the SPI transfer (perhaps they're done in parallel)?

How can I make sure that the PID ISR is called before the SPI transfer begins? See screenshot below.

[wlan]

Additional note: I see that the execution of the PID ISR is delayed sometimes. How is that possible if the interrupt already has priority 0? I don't see any other IRQs that high.

[kerryzhou]

Hi @wlan ,

   Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you.

  What's the PID interrupt you are meaning? PIT timer interrupt?

   If it is the PIT interrupt, it is controlled by the timer, the PIT HW IP, not the software.

  I think, you need to check whether the PIT interrupt timer is correct or not, not only check the position with the SPI transfer.

  Do you have any other interrupt in your project? Whether that Interrupt handler code is long or not? As if the other interrupt have higher priority, it may let the PIT interrupt delay to be called, you need to check your whole project situation, you even can do a simple project, which just contains the PIT, SPI situation.

Wish it helps you!

If you still have questions about, please kindly let me know.

Best Regards,

Kerry