Need to disable MMDC arbitration to get the DDR Stress Test to not fail...

[MichaelV]

Hi,

I've got a couple of iMX6 Quad modules here from a large manufacturer in a 1 GB and 2 GB version. On both of these I have to disable MMDC arbitration to get the DDR Stress Test to succeed. With MMDC arbitration enabled (MAARCR left as reset default, bit 26 ARCR_ARB_REO_DIS cleared), the DDR Stress Test almost always fails in the first iteration (and if not; in the 2nd iteration):

DDR Stress Test Iteration 1
Current Temperature: 47
============================================

DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
test1 Address:   0x21b80080
Data initally read was:   0x55555555
Data re-read is:          0x55555555
But pattern was: 0x804f2578
Bit location:    0xd51a702d
Error: failed to run stress test!!!

If I add the following (after setting the CS end and before writing to MDCTL) in the script:

setmem /32	0x021b0040 =	0x00000047	// CS0_END 

//setmem /32  0x021b0400 =    0x514201F0  // MAARCR reset default - This causes random pattern test failures in the NXP DDR Stress Test Tool
setmem /32  0x021b0400 =    0x554201F0  // MAARCR Disable MMDC arbitration - This allows the NXP DDR Stress Test to run forever without errors

setmem /32	0x021b0000 =	0x841A0000	// MMDC0_MDCTL

...then the Stress test continues without errors indefinitely.

I have worked on a lot of different iMX6 designs (>70) and I have NEVER seen any board or module require MMDC arbitration to be disabled.

What could be the reason for this?

[MichaelV]

Ok, turns out these modules are actually DQPlus modules.

The DQP Script aid sets MAARCR to 0x14420000 (reset default is 0x514201F0).

Weird things are being set and cleared. I would love to hear from NXP why:

• ARCR_SEC_ERR_LOCK: cleared
• ARCR_SEC_ERR_EN: set, changed to cleared: This bit defines whether security read/write access violation result in SLV Error response or in OKAY response. IMHO this should NOT be cleared!
• ARCR_EXC_ERR_EN: set
• ARCR_ARB_REO_DIS: cleared, changed to set: MMDC arbitration and reordering controls disabled (was enabled)
• ARCR_REO_DIS: cleared
• ARCR_RCH_EN: set, changed to cleared:This bit defines whether Real time channel is activated and bypassed all other pending accesses, So accesses with QoS=='F' will be granted the highest priority in the optimization/reordering mechanism. Default value is 0x1 - encoding 1 (Enabled), 0 = normal prioritization, no bypassing, 1 = accesses with QoS=='F' bypass the arbitration
  
• ARCR_PAG_HIT: 0x04
• ARCR_ACC_HIT: 0x02
• ARCR_DYN_JMP: 0x01, changed to 0x00: ARCR Dynamic Jump. Each time an access is not chosen by the optimization/reordering mechanism then its dynamic score will be incremented by ARCR_DYN_JMP value.
  NOTE: Setting ARCR_DYN_JMP may cause starvation of low priority accesses. NOTE: ARCR_DYN_JMP must be smaller than ARCR_DYN_MAX. Default ARCR_DYN_JMP value is 0x0001 - encoding 1
• ARCR_DYN_MAX: 0x0F, changed to 0x00: ARCR Dynamic Maximum. ARCR_DYN_MAX is the maximum dynamic score value that each access inside the optimization/reordering mechanism can get.
  
• ARCR_GUARD: 0x00

As you can see, the value of DYN_JMP is actually in violation of the requirement that "ARCR_DYN_JMP must be smaller than ARCR_DYN_MAX". Currently they are equal (both 0)...

I would love to hear why MAARCR is setup like this in the D/Q Plus DDR script aid.

I've also tested with an MAARCR value of 0x54420010 (this leaves ARCR_SEC_ERR_EN set as per reset default, and it now follows the requirement of ARCR_DYN_JMP to be smaller than ARCR_DYN_MAX). This also works.

As a final step, I set MAARCR to the reset default, apart from bit 26 which disables MMDC arbitration, and this bit is indeed the key. When bit 26 of MAARCR is set (meaning MMDC arbitration is disabled) the DDR scripts works. With it left cleared (as reset default, meaning MMDC arbitration enabled), the DDR scripts fail to complete the DDR Stress Tests.

[MichaelV]

NXP engineers, could you please reply to my questions?