I am trying to nand boot my mx6 based custom board. I have written the FCB manually. I can see the IVT header being placed at 0x907400
S:0x00907400: 0x0D100000 0x00040200 0x00000908 : ............
S:0x0090740C: 0x91800000 0x90C00907 0x8EC00907 : ............
S:0x00907418: 0x00000907 0x00000000 0x8EC00000 : ............
S:0x00907424: 0x00000903 0x0000000B 0x0D200000 : .......... .
S:0x00907430: 0x0CC40080 0x00004040 0x00000000 : ....@@......
S:0x0090743C: 0x00000000 0x00000000 0x00000000 : ............
S:0x00907448: 0x00000000 0x80000000 0x00000000 : ............
S:0x00907454: 0x00000000 0x00000000 0x00000000 : ............
S:0x00907460: 0x00000000 0x00000000 0x00000000 : ............
S:0x0090746C: 0x00000000 0x00000000 0x00000000 : ............
But I could not get my SPL loaded and executed. I have Nullified the DBBT so that ROM code does not search for the BAD blocks in the NAND. I have also tested kobs-ng tool here are the steps
dd if=SPL of=SPL-nand bs=512 seek=2
kobs-ng init -v SPL-nand
After it when I reboot the board it does not boot SPL neither fall back to USB boot which means that FCB is good to go. I cannot see the IVT header at 0x907400 in this case when I connect through JTAG
where as when I use my FCB command it fall backs to usb boot :smileysad:.
Moreover you can see that at address 907400 it is not the exact IVT header.The first four bytes are 402000D1 in the hexdump of the SPL
I have loaded the same SPL from usb tool and it works. I am using dstream and ds5 for JTAG debugging.
Am i missing something here ?
Solved! Go to Solution.
the problem was with the DCD table of SPL. After enabling NAND clocks I was able to boot from NAND
Thanks Igor for your help and time.
Kind Regards
Hi adnan
as IVT header is wrong at address 907400, there may be hardware
issues, one can try attached simple read/write page nand test.
In general one can boot from sd and write uboot with kobs-ng
using as example mfg tools scripts ucl2.xml, *.vbs for sabre-ai
board (it has nand). Recommended to use uboot built for that boards,
check latest BSPs
Board Support Packages (29)
L3.14.52_1.1.0_MX6QDLSOLO (REV L3.14.52_1.1.0)
Programmers (Flash, etc.) (8)
IMX6_L3.14.52_MFG_TOOL (REV L3.14.52_1.1.0)
Best regards
igor
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I have already tested kobs-ng tool. Here is the procedure
1) NAND boot falls back to USB boot
2) Connect JTAG
3) Run SPL (u-boot-spl)
4) Run u-boot.imt (u-boot)
5) Use tftp to load kernel and dtb
6) bootz
when the kernel is up I can see /dev/mtd0 device.
from kernel I use
dd if=SPL of=SPL-nand bs=512 seek=2
kobs-ng init -v SPL-nand
After reboot the board does not boot SPL. However it even does not even fall back to USB which means it is working but 50%.
you mentioned the IVT header is not correct. What i understand is, it should be 0x402000D1 at address 0x907400, right ?
I tried mfg tool but board did not get detected. I am using yocto, is there a way to test the nand in it ?
one can test NAND using board configuration for sabre-ai boards, refer to
attached Release NotesTable 3. Kernel and device tree configurations
and Yocto Guide sect.5.1 Build configurations.
Also NXP/FSL uboot does not use SPL.
Board Support Packages (29)
L3.14.52_1.1.0_MX6QDLSOLO (REV L3.14.52_1.1.0)
~igor
But my custom board deviates from the sabreai iomux by a great deal. It would require setting up those muxes in uboot and kernel.
Is there any way I can port this nand test ?
you mentioned the IVT header is not correct. What i understand is, it should be 0x402000D1 at address 0x907400, right ?
right, you will have to port it for using sabreai
configuration. IVT header is described in sect.8.6.1.1 Image Vector
Table Structure iMX6DQ RM
With a few changes in the FCB i was able to locate my IVT header at correct location 0x907400.
S:0x00907400: | 0x402000D1 | 0x00908000 | 0x00000000 | : | .. @........ |
S:0x0090740C: | 0x00907918 | 0x0090790C | 0x009078EC | : | .y...y...x.. |
S:0x00907418: | 0x00000000 | 0x00000000 | 0x009038EC | : | .........8.. |
S:0x00907424: | 0x0000B000 | 0x00000000 | 0x400800D2 | : | ...........@ |
I cannot see the SPL code at address 0x00908000. which is the entry point of the application.
What happens after the IVT is placed at 907400 or at what stage is the application copied from NAND to IRAM/DRAM ? I am sure you cannot share the ROM code but can atleast guide me through the stages.
Regards
after locating IVT ROM copies data according to
Figure 8-21. Image Vector Table i.MX6DQ Reference Manual
http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf
You can check if some data are present in DDR
("Dest. Memory" in Figure 8-2)and if DDR is correctly initialized
(just read/write to it with jtag)
~igor
the problem was with the DCD table of SPL. After enabling NAND clocks I was able to boot from NAND
Thanks Igor for your help and time.
Kind Regards