Host OS: Windows 10
Debug Probe: Segger J-link Ultra+
SDK Version: 2.7.0
Eval Board: 8MMINILPD4-EVK
Introduction:
I am having some difficulty debugging the SDK's hello world program from DDR on the Cortex M4. Similar issues have arisen before for others on the imx6, as documented here and here . In the referenced issues, the jtag debugger was setting software breakpoints in DDR instead of the cache, leading to some undesirable inconsistencies when the cache was enabled.
In my case, the debugger immediately steps to 0xdeadbeef on the very first instruction of the reset vector. The reset value of the LMEM enable at 0xe0082000 is zero according to the TRM. Furthermore, the hello world program does not enable the cache until the SystemInit call. For these reasons, I am inclined to think that my problem is a bit different from the imx6 issues.
GDB works as desired when running the program out of TCM.
Does anyone have an inkling as to what is going on here?
To reproduce:
-follow setup steps from the getting started guide.
-eliminate cache setup code as outlined in one of the linked posts. (I only included this for completeness. This step should not affect any behavior since execution never reaches the cache initialization section.)
-follow the steps on the getting started guide to load the program
for both the ddr_debug and debug images.
-attempt a single step.
Below are a pair of screenshots showing the differing behavior for DDR and TCM based code. I reset power on the unit between tests.
DDR:
TCM RAM:
EDIT: I should also add that the DDR program runs normally when no breakpoints are enabled.
