Load capacitors for i.MX8 DXP oscillators

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Load capacitors for i.MX8 DXP oscillators

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RobertoVigliarolo
Contributor I

Hi,

in this document i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide (Rev. 2.3p, 02/2021) there are suggestion on how to change internal oscillators load capacitors: “3.9.3 Internal load capacitor trimming (24 MHz and 32.768 kHz)”.

I need an explanation for this sentences: “Note: The impact of stray capacitance Cstray 1), typically 16 pF 2), should be included when programming trimmed values” and

” 1) Cstray is understood as the cumulative effect of the typical PCB parasitic capacitance and the on-chip and package capacitances.2) The value is per-pin and applicable only for the pins of the 24 MHz crystal.”

The value of 16 pF per pin is uncommon and seems very high.

For this reason, I looked up in the relevant IBIS file for the on-chip and package capacitances and this is what I found:

[Package]

|               typ                    min                 max

C_pkg      1.224e-12        7.498e-13       3.887e-12

[Pin]     Signal_name               model_name                              R_pin          L_pin        C_pin

AP32        RTC_XTALI            IO_20UM_RES_ANAF_1V8     0.54741       3.327e-9     1.416e-12

AM32        RTC_XTALO          IO_20UM_RES_ANAF_1V8     0.47797       2.858e-9     1.315e-12

AP34        XTALI                      IO_20UM_RES_ANAF_1V8     0.54935        3.26e-9     1.467e-12

AM34        XTALO                   IO_20UM_RES_ANAF_1V8     0.48625       2.947e-9     1.386e-12

[Model Selector] IO_20UM_RES_ANAF_1V8

IO_20UM_RES_ANAF_1v8_mt   IO_20UM_RES_ANAF_FC_LIN_NXP, 1.8V

[Model]  IO_20UM_RES_ANAF_1v8_mt

Model_type Terminator

C_comp                0.5533pF          0.5015pF            0.6178pF

|C_comp_pullup   0.2711pF          0.2913pF            0.2556pF

|C_comp_pulldown   0.2605pF          0.3048pF            0.2242pF

From this information it seems that the typical capacitance per oscillator pin, both 32K and 24M oscillators, is about 1.9 pF.

For the typical PCB parasitic capacitance, I estimate a microstrip trace with length of 10 mm per pin.

Looking at my field solver, this capacitance is 1.5064065e-010 Farads/Meter * 0.01 meters = 1.5 pF

So, the total stray capacitance per pin should be 1.9 pF + 1.5 pF = 3.4 pF. Accounting for others not considered parasitics (e.g. pads) I use the value of 4 pF.

I need to use crystals calibrated for a load capacitance of 9 pF, so I plan to burn in the OTP fuse the value associated with: 9 pf * 2 – 4 pF = 14 pF.

The values to program in the OTP fuses are not in the reference manual, but only in the document referred above, and so I will program the following in fuse row index 768:

BRD_OSC_CAP_TRM_VALUE_32K[19..16] :           1111       (14 pF)

BRD_OSC_CAP_TRM_VALUE_24M[3..0] :              0111       (14 pF)

Can you please tell me if my reasoning is correct and, if it is so, add in the reference manual the information to be programmed in all the OTP fuses?

Finally, I have another question: what is the worst case tolerance of the internal load capacitor?

The deviation from nominal value will pull away the oscillator frequency: this can cause problems for Ethernet applications that require an accuracy of +/- 50 ppm.

Best regards,

Roberto Vigliarolo

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Yuri
NXP Employee
NXP Employee

@RobertoVigliarolo 
Hello,

    Please use the value of 16 pF is Your considerations:
  "In the latest HDG, we provided 16 pf stray cap for 24Mhz which was from TE/PE’s test
and customers’ crystal matching test results".

Regards,
Yuri.

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