Linux based Device driver for RGB Display

[SAVIOR]

Since over 3 years we have been successfully using a RGB display for our main-board based on NXP-i.Mx6UL processor with embedded Linux version HardKnott.

Now we are making a new main-board based on NXP-i.Mx9352 processor with embedded Linux version Mickledore. We want to retain the RGB display which is used in our older board.

Our project is stuck because display is not working with our new board based on i.Mx9352, although the backlight of the RGB is coming on, nothing is getting displayed.

We need the Linux based device driver for our 5 inch RGB parallel display is 5 inch TFT of Sinda : SDT05004CT-40, having TFT driver IC as OTA7001A/OTA9960A.

Attached herewith is the technical specification of the RGB display and also the section of the schematic of our new main-board for display.

[Zhiming_Liu]

Hi @SAVIOR 

We can't  provide the driver about this TFT driver IC. How do you drive this panel on i.MX6ULL? The porting steps should be similiar on i.MX93.

Best Regards

Zhiming

[SAVIOR]

As informed earlier, we are making our new main-board on i.Mx9352 based on Yocto Version:4.2 (Mickledore, Kernel Ver:6.1.55), while our existing main-board on i.Mx6UL is based on Yocto Version:3.3(Hardknott, Kernel Ver:5.10.72).

We are looking for section of code required for making the parallel RGB display work in i.Mx9352 based on Mickledore. We need help on code with equivalent values, as was available in i.Mx6UL.

To clarify our requirement, we are showing below the section of .DTS file which is being used to handle the display in i.Mx6UL:

&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
display = <&display0>;
status = "okay";
display0: display {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <25344000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <40>;
hback-porch = <88>;
hsync-len = <48>;
vback-porch = <32>;
vfront-porch = <13>;
vsync-len = <3>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
>;
};
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
/* used for lcd reset */
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
>;
};

Below is the section of code for RGB display in the .DTS file available in the BSP of i.Mx9352 which is not working :
&lcdif {
status = "okay";
 assigned-clock-rates = <445333333>, <148444444>, <400000000>,
 <133333333>;
};

[Zhiming_Liu]

Hi @SAVIOR 

Please refer the content of /arm64/freescale/imx93-9x9-qsb-ontat-wvga-panel.dts, set correct display format  in parallel_disp_fmt.

The most important is about clocks, please refer below steps.