Hi.
We're trying to run the DDR Stress Test on a custom iMX8QM board with LPDDR4.
Using ER14 of DDR Stress Test and V23 of the RPA excel sheet.
We get the following message in the DDR Stress test when downloading.
"MX8 DDR Stress Test Version: ER14
Built on Mar 27 2020 12:19:30
*************************************************************************
--Set up the MMU and enable I and D cache--
- This is the Cortex-A72 core
Adjusting CA72 cache latency
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug
- VMCR Check:
- ttbr0_el3: 0x13d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1124
- MMU and cache setup complete
*************************************************************************
ARM Clock(CA72): 1596MHz
DDR Clock: 1596MHz
============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 16, col size: 10
Two chip selects are used
Number of DDR controllers used on the SoC: 2
Density per chip select: 2048MB
Density per controller is: 4096MB
Total density detected on the board is: 8192MB
Note: As this SoC has more than one DDR Controller, the calculated
density assumes all controllers are being used. Adjust the tested
density per your board configuration if not all controllers are used
********************************************
WARNING! DDR training errors were detected on DDRC 0!
DDR_PHY_PGSR0 = 0x806cc07f
DQS Gate training error detected
Write Leveling training error detected
VREF training error detected
Write DQS2DQ training error detected
Recheck DDR initialization
********************************************
********************************************
WARNING! DDR training errors were detected on DDRC 1!
DDR_PHY_PGSR0 = 0x806cc07f
DQS Gate training error detected
Write Leveling training error detected
VREF training error detected
Write DQS2DQ training error detected
Recheck DDR initialization
********************************************
============================================
MX8QM: Cortex-A72 is found"
I've checked the connections between iMX8 and LPDDR4 and verified in RPA Excel sheet and it looks correct. I've tried changing the ODT and drive strenghts without any luck.
Schematic is copied from MEK with some minor DQ changes in same bytelane.
We've used the .cfg file from RPA and put that in the SCFW .CFG file for 1.6GHz and also used the script from the RPA excel for the DDR Stress test.
What could be the cause of this?
Hi Viktors94,
The reason for this issue may be wrong memory connections or incorrectly configured "BoardDataBusConfig" parameters in the RPA tool.
Looking into the lines DQ lines DDR_CH1_DQ22 it appears declared on the BoardDataBusConfig incorrectly:
So this can be causing the error.
Regards,
Israel.
