IMX7 SPI DMA request

[cedricjehasse]

Hi,

we have an SPI tft display connected to ECSPI3. We're using fbtft for the display driver.

To avoid a gap after every 8bit transfer on SPI, i've backported changes to spi-imx.c from a vanilla 4.14 kernel to the 4.9.88_2.0.0_ga.

When dma is enabled on ecspi3 i get "spi_imx 30840000.ecspi: I/O Error in DMA TX" errors when loading the fbtft driver.

fbtft first sends short transfers to spi which are sent in PIO mode by the SPI driver, then it sends bigger blocks of data sent in DMA mode.

To check what's wrong i mad a script that prints the DMA requests register (SDMAARM_EVT_MIRROR) in a loop when modprobing the driver. The register is either 0x00000000 or 0x00000020.

It seems it's only generating eCSPI3 Rx requests, no Tx requests.

I've found out if i modify the driver to only set ECSPIx_DMAREG for DMA transfer, and clear it for PIO transfers. I don't see have the problem. And polling the DMA request register sometimes shows 0x00000030, meaning eCSPI3 Tx request bit is set.

Is it possible the eCSPI3 Tx DMA request hasn't been set, on Tx empty? Or SDMA has cleared this DMA request before a SDMA transfer was programmed? 

Below is the change that solves the problem

from this:

writel((MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
          MX51_ECSPI_DMA_TX_WML(tx_wml) |
          MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
          MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
          MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
‍‍‍‍‍

to this:

writel((spi_imx->usedma ? MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
          MX51_ECSPI_DMA_TX_WML(tx_wml) |
          MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
          MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
          MX51_ECSPI_DMA_RXTDEN : 0), spi_imx->base + MX51_ECSPI_DMA);
‍‍‍‍‍

thanks for the help,

Cedric

[caglarabidin]

Hi  Cedric,

 I am trying to interface spi-tft screen by using fbtft on imx6 with yocto 4.9.88 kernel. Driver is loaded and worked without giving an error, but i could not get enough data rate for video display even at  30MHz-60MHz spi clock speeds.when i inspect data from scope, i saw there is a  ~50us gap between bursts.  I wonder have you encountered with such a problem? Do you have any suggestion ?

Regards,

[darsh_dev]

Hi caglarabidin‌,

Did you get any resolution for the ~50us gap in framebuffer bursts? I am also facing similar issue.

Regards,

Darshak

[caglarabidin]

Hi

Unfortunately I could not get  good performance .I only got  5 fps and glitchy display. I decided to use parallel RGB interface instead of SPI.

Regards,

[Bio_TICFSL]

Hello Cedric,

I'm assuming you're referring to the eCSPI3 on i.MX51, while on the i.MX51 reference manual, I can't see the eCSPI3 module.

(To support SDMA transfer on one peripheral, there should be HW connection between the peripheral and the SDMA controller.
  1. DMA event should be mapped
  2. Peripheral FIFO should be accessible for the SDMA controller
 For chip like i.MX6QD, the eCSPI1-5 all support the SDMA transfer.)

Regards

[cedricjehasse]

Hello,

it's eCSPI3 on a i.MX7.

The datasheet says the scheduler detects the rising edge of DMA requests.

What happens if the DMA channel is disabled at the time the DMA request is set, and the DMA channel gets enabled when the DMA request signal is already active? Will the scheduler set the channel pending flag, or is this only set after a new edge detection on the DMA request signal?

Thanks,

Cedric