I have a device that needs to be put into SPI mode by doing the following:
1. During startup, the module toggles DRDY to indicate to the host that it is awake and polling the SPI interface.
2. Having detected toggling on the DRDY signal, the host asserts the SPI CS and enables the SPI clock signal, SCLK.
3. The module detects the SPI SCLK and enables the SPI interface. When the host has received +STARTUP from the module, it is then ready to accept AT commands over the SPI bus.
In my device tree I have set the DRDY signal to CSPI_RDY:
MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x0b0b0
>;
};
I can't really find a good explanation of how exactly CSPI_RDY behaves when I use spidev.h to send data over the spi-bus. Is there any way that I can poll the ECSPI1_RDY bit and then send some data or is this already done automatically by the imx spi driver?
I found this in the Freescale documentation:
"Serial Data Ready signal - This input signal is used for hardware control only in master mode. It indicates that external SPI slave is ready to receive data. It will edge or level trigger a CSPI burst if used. If the hardware control enabled, CSPI will transfer data only when external SPI slave is ready."
So then I assume that because it is in my device tree - the polling is handled automatically. Thus I don't have to worry about timing anything - I just reset the external device, send some SPI data and the SPI controller will take care of waiting for the CSPI_RDY bit?
