IC9881C IC display timing variables IMX8MM

[wdunkley]

I'm not sure what some of the timing variables are.

In raydium-rm67191.c this is what I've changed

static const struct display_timing default_timing = {
.pixelclock.typ = 66770000,
.hactive.typ = 800,
.hfront_porch.typ = 16,
.hback_porch.typ = 48,
.hsync_len.typ = 2,// I'm not sure what this value is, should it be the width?
.vactive.typ = 1280,
.vfront_porch.typ = 8,
.vback_porch.typ = 4,
.vsync_len.typ = 2,// I'm not sure what this value is, should it be the width?
.flags = DISPLAY_FLAGS_HSYNC_LOW |
DISPLAY_FLAGS_VSYNC_LOW |
DISPLAY_FLAGS_DE_LOW |
DISPLAY_FLAGS_PIXDATA_NEGEDGE,// I'm not sure where to find out which flags to set
};

This is what I changed in panel-raydium-rm67191.c

static const struct drm_display_mode default_mode = {
.clock = 66770,//I didn't see any documentation about this value being devided by 100 but that how it was befor
.hdisplay = 800,
.hsync_start = 800 + 20,//What are all these +20 and +2 numbers
.hsync_end = 800 + 20 + 2,
.htotal = 800 + 20 + 2 + 34,
.vdisplay = 1280,
.vsync_start = 1280 + 10,
.vsync_end = 1280 + 10 + 2,
.vtotal = 1280 + 10 + 2 + 4,
.vrefresh = 60,
.width_mm = 143,
.height_mm = 228,
.flags = DRM_MODE_FLAG_NHSYNC |
DRM_MODE_FLAG_NVSYNC,
};// not sure about the flags

Any help would be very appriciated.

[wdunkley]

 Deleted

[Zhiming_Liu]

Hi

1.hsync_len.typ = 2,// I'm not sure what this value is, should it be the width?

--->hsync width

2.vsync_len.typ = 2,// I'm not sure what this value is, should it be the width?

--->vsync width

3..flags = DISPLAY_FLAGS_HSYNC_LOW |
DISPLAY_FLAGS_VSYNC_LOW |
DISPLAY_FLAGS_DE_LOW |
DISPLAY_FLAGS_PIXDATA_NEGEDGE,// I'm not sure where to find out which flags to set

--->DISPLAY_FLAGS_HSYNC_LOW: hsync low level active 

DISPLAY_FLAGS_DE_LOW:Data enabe signal is low level

DISPLAY_FLAGS_PIXDATA_NEGEDGE:drive data on neg,edge

4..clock = 66770,//I didn't see any documentation about this value being devided by 100 but that how it was befo

pixel clock = (hactive + hfront_porch + hsync_len + hback_porch)x (vactive + vfront_porch + vsync_len + vback_porch)x frame rate

pixel clock = (1080 + 20 + 2 +34) × (1920 + 10 + 2 + 4) x 60

pixel clock =132000000(roundedup)

[wdunkley]

if hsync_len.typ should be set to hsync width, shouldn't it be 16 and vsync_len.typ = 4. It seems like it'd change the pixel clock. Is there a difference between the data clock and the pixel clock?