I’m trying to interface SLIC IC 32287 with iMX6q processor.

[snehaljadhav]

The SI32287 provides SPI and PCM interface to host. Also, the SPI interface pins SCLK, SPI_MOSI, SPI_MISO, & CHIP SELECT are mapped to Processors SPI port and the PCM interface pins MOSI, MISO, PCLK and frame Sync are mapped to the processor AudioMux port5(act as PCM).

The minimum PCLK frequency for PCM interface of SLIC IC should be 512KHz according to the datasheet. PCLK signal is mapped to TXC pin of AUDMUX Port 5 of processor.

Will the processor be able to generate 512KHz of frequency at TXC pin?

Also, the PCLK frequency is dependent on the frame sync. My frame sync frequency is fixed of 8KHz.

Is the configuration possible for frame sync of 8KHz, Word-length of 64bits(for dual channel of SLIC) and PCLK of 512KHz?

[abhijeet_ghodga]

Hi Igor,

After setting up the clock parameters and following up with your resources, we have to now integrate an embedded audio system using primarily PCM codec, and receive data from Si32287. (PCLK=512kHz and FSync=8kHz)

We have made changes to SSI node in device tree, and added support for imx-itel in si476x.c driver file in the Yocto build. But, we do not know how to proceed with integration of the codec with the processor. The voice signal from the telephone gets through the DSP block inside the IC and should be received on the iMx side in a 16-bit codec format. 

There are a few approaches I have thought of i.e. using Dynamic PCM feature of Linux to create DAI,

or to create a dummy node that can create a dai link.

Thank you.

Best,

Abhijeet

[igorpadykov]

Hi Snehal

max.TXC  frequency can be found in sect.4.12.20 SSI Timing Parameters i.MX6DQ Datasheet

http://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf

Options for frame sync are described in sect.61.8.4.1 SSI Clock and Frame Sync Generation

i.MX6DQ Reference Manual

http://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf

Best regards
igor
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[snehaljadhav]

Hi igorpadykov,

I need the frequency of 512kHz to be generated at TXC pin which requires to set the clock sources of AUDMUX. The clock sources to AUDMUX is provided by Clock Controller Module where PLL4 is referenced as Audio PLL.

The audio PLL uses a reference frequency as 24MHz and the output freuency range is from 650MHz to 1.3GHz. To get the frequency of 512kHz, I need to program the fields in the registers CCM_ANALOG_PLL_AUDIO and CCM_ANALOG_MISC2 includingly set the post dividers.

I am using jethro version of yocto to build the BSP. The machine used is imx6qsabred. So as to create a patch file to configure the registers in device tree, I am trying to find the default settings of these CCM registers.

How to find these registers to configure it

[igorpadykov]

Hi Snehal

you should configure it yourself based on description in suggested documents

and examples described in linux documentation provided on nxp software link

i.MX Software|NXP 

As starting point one can use description of codec drivers provided in Chapter 28
Advanced Linux Sound Architecture (ALSA) System on a Chip (ASoC) Sound Driver

attached Linux Manual.

Also you can get full solution using extended software support provided with  NXP Professional Services

NXP Professional Services|NXP 

Best regards
igor

[snehaljadhav]

Thanks igorpadykov for the solution.

[igorpadykov]

Hi Snehal

may be useful to check AN4952 i.MX 6 Audio Clock Configuration Options
https://www.nxp.com/docs/en/application-note/AN4952.pdf

Best regards
igor

[snehaljadhav]

Thank you.