I.MX8MP ISI maximum supported width

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I.MX8MP ISI maximum supported width

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btogorean
Contributor I

Hi NXP community,

I am trying to bring-up a system that is composed of an I.MX8MP eval board from SolidRun and a custom MIPI 4 lane camera. The particularity of the camera is that the data output format is RAW12 packed with resolution of 32768 width by 8 height at 30 FPS.

A image describing the MIPI data can be seen attached bellow.

In the first iteration I would like to use only the DMA capability of the I.MX8MP ISI to store the captured frames in RAM memory. I would like to bypass the processing (No Scaling and No Color Conversion) but from my understanding the ISI is capable to capture images with a line with up to 2K or 4K with buffer chain configuration.

Even the CHNL_IMG_CFG register has allocated only 13 bits for setting width or height.

So is my understanding correct and this camera setup is not possible with I.MX8MP or I got it wrong?

Thank you

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joanxie
NXP TechSupport
NXP TechSupport

refer to the mipi csi spec:

MIPI CSI Slave block needs the configuration of Image resolution to measure one line length exactly and detect frame end. Vertical resolution register has 16bits (16’h0001 ~ 16’hFFFF) Horizontal resolution register has 16bits (16’h0004 ~ 16’hFFFC).

so for the mipi csi can support this , but for ISI, pls refer to the 13.4.8.1.5 Channel Image Configuration (CHNL_IMG_CFG), which is the register for ISI width and height, refer to the register:

28-16
HEIGHT

Input image height (lines)
This field provides the height of input image in terms of number of lines for both cases when the image is input from pixel link or from memory. Default height is 1080 lines

12-0
WIDTH

Input image width (pixels)
This field provides the width of input image in terms of number of pixels for both cases when the image is input from pixel link or from memory. Default width is 1920 pixels.

so I don't think ISI can support 32768 pixels as width

 

 

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joanxie
NXP TechSupport
NXP TechSupport

for the ISI of IMX8MP:

The ISI includes the following features:
• Supports one source of 4K resolution at 30 fps (24bpp).
• Supports up to 2K resolution at 30 or 60 fps (24bpp) on each channel.
• Input sources supported:
• 2 pixel link interfaces running in parallel that can interface to 2 camera sensors.
• System Memory (AXI master; internally converted to Pixel Link Interface).

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btogorean
Contributor I

Thank you joanxie but that information I could get too from the Reference manual.

My question is if I.MX8MP ISI support such wide lines? The total pixel resolution of a frame is 262,144 pixels, which is well under 4K or even 2K. But as I stated in my first post the width of one line is 32768 pixels.

Thank you

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joanxie
NXP TechSupport
NXP TechSupport

refer to the mipi csi spec:

MIPI CSI Slave block needs the configuration of Image resolution to measure one line length exactly and detect frame end. Vertical resolution register has 16bits (16’h0001 ~ 16’hFFFF) Horizontal resolution register has 16bits (16’h0004 ~ 16’hFFFC).

so for the mipi csi can support this , but for ISI, pls refer to the 13.4.8.1.5 Channel Image Configuration (CHNL_IMG_CFG), which is the register for ISI width and height, refer to the register:

28-16
HEIGHT

Input image height (lines)
This field provides the height of input image in terms of number of lines for both cases when the image is input from pixel link or from memory. Default height is 1080 lines

12-0
WIDTH

Input image width (pixels)
This field provides the width of input image in terms of number of pixels for both cases when the image is input from pixel link or from memory. Default width is 1920 pixels.

so I don't think ISI can support 32768 pixels as width

 

 

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btogorean
Contributor I

Thank you joanxie for your answer,

This clarify my question.

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