How to get 8-bit MIPI-DBI parallel signal out of MIPI-DSI host controller?

[dehuanxin]

I have a parallel LCD display that needs to be connected to IMX6Q SoC.

The LCD uses ILI9486L driver IC. This driver IC supports 8/9/16 data bus and MIPI-DBI protocol.

I've been researching for more than a week trying to configuring IPUv3 to support this LCD display (async smart display, sys80 bus, DBI commands) but no luck.

IP cores like ADC (async display controller) is not present on IMX6 unlike IMX53.

However, digging deeper into IMX6Q reference manual I found out MIPI-DSI host controller has full support for DBI protocol.

My question: is there a way to skip the serialization process of DSI host controller and redirect the parallel data out of the SoC, so that it can drive the LCD directly?

Thanks.

[igorpadykov]

Hi Dehuan

DSI Host Controller is a digital core that is designed to implement all protocol functions

defined in the MIPI DSI Specification. I am afraid there is no way to skip the serialization

process of DSI host controller.

Best regards

igor

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[dehuanxin]

Hi, igor,

Thanks for following all my questions.

I'm still very confused about how to get a 8-bit MIPI-DBI Type-B LCD display working with IMX6Q.

What I found out today is:

1) IPUv3h in IMX6Q lacks the "direct display access" capability compared with IPUv3m in IMX53, which makes it very difficult to write initialization commands to the LCD, if possible at all. Although LLA (low level access) is preserved, related documentation is almost non-existent.

2) As is defined by MIPI-DBI, to get the LCD ready for incoming data, a "memory write" command (op_code=0x2C) needs to be written with RS (high=write data, low=write command)pin pulled to low. The RS signal can be implemented using wave form generator in DI, but I'm very unsure if the 0x2C command can be easily generated by LLA or other methods, since using a frame-ready interrupt to trigger CPU to write it is not possible due to above limitation.

3) 41.4.2 in IMX6DQRM states that DSI host controller accepts DPI and DBI inputs, but offered little information on how it is connected to IPU.

    At the same time 7.3 in Linux Reference Manual Freescale Yocto L3.14.52 says that DSI host controller does not support DBI mode.

To this point I have strong feeling that DBI protocol is completely dropped from IMX6Q. Linux driver for it not only doesn't exist but is extremely hard to write due to above limitations and lack of documentation.

If I don't make any progress on making IPU support MIPI-DBI type B this week, I would try bridging MIPI-DPI to MIPI-DBI using a FPGA.

Good luck to me.

Dehuan