How can I set SCLK to (serial clock root/2) for DDR mode in FlexSPI?

[takayuki_ishii]

Hello community,

To use DDR mode in FlexSPI with 66MHz SCLK output, is it need to set

flexspi_clk_root=133MHz(2x 66MHz) and MCR0[SERCLKDIV] = 001 (Divided by 2)?

Or MCR1[HSEN] bit can use  to output SCLK as half of serial clock root for DDR mode?

No matter what documentation I look at, I can not find any information

about MCR1[HSEN] bit of FlexSPI both imx and imxrt.

Best regards,

Ishii.

[Manuel_Salas]

Hello @takayuki_ishii ,

I am not sure what processor are you using, but for i.MX8MP:

If you set MCR0[SERCLKDIV] = 001 (Divided by 2), the clock of the FlexSPI will divide by 2.

In this case, you need to set the MCR0[HSEN] bit. This bit enables the divide by 2 of the clock to external serial flash devices (A_SCLK/B_SCLK) for all commands (for both SDR and DDR mode). FlexSPI need to be set into MDIS mode before changing value of HSEN. Otherwise, it is possible to cause issue on internal logic/state machine. 

about of MCR1[HSEN], this register does not exist, I guess your refer to MCR0:

This information is in the Reference Manual.

I hope I had answered your questions.

Best regards!

[takayuki_ishii]

Hello @Manuel_Salas 

Thank you for your replay.

I'm using imx93. and HSEN bit is MCR0 register is correct.

In Table 121. clock root table of IMX93 Reference manual.

Max frequency of flexspi1_clk_root is 400MHz in normal mode.

Which is correct setting to use x_SCLK=66MHz with DDR mode?

 1) MCR0[SERCLKDIV] = 010(Divided by3), MCR0[HSEN]=1(half-speed clock enable) :

400MHz /3 /2=66MHz

 2) MCR0[SERCLKDIV] = 101(Divided by6), MCR0[HSEN]=0(half-speed clock disable)  :

400MHz /6 /1 = 66MHz

Or if it have some limitation "This clock runs at half the frequency of serial clock root in DDR mode" 

In table 10-3 you attached,

 3) flexspi1_clk_root=133MHz, MCR0[SERCLKDIV] = 001(Divided by2),

MCR0[HSEN]=0(half-speed clock disable) : 133MHz /2 /1 = 66MHz.

I would like to know when to use HSEN bit.

Best regards,

Ishii.