Flexcan doesn't execute soft reset

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Flexcan doesn't execute soft reset

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wolnet
Contributor III

I use the xenomai realtime driver for flexcan but function flexcan_chip_start never worked successfull because the

softreset never finished.

/* enable module */

    flexcan_chip_enable(priv);

    reg_mcr = flexcan_read(&regs->mcr);          ->   Logmessage: rtcan0: regs->mcr d0c00000 reg_mcr 0x7980000f

    /* soft reset */

    flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);

    udelay(10);

    reg_mcr = flexcan_read(&regs->mcr);

    if (reg_mcr & FLEXCAN_MCR_SOFTRST) {

        rtcandev_err(dev,

                 "Failed to softreset can module (mcr=0x%08x)\n",   

                 reg_mcr);                                   ->   Logmessage: rtcan0: Failed to softreset can module (mcr=0x5b80000f)

        err = -ENODEV;

        goto out;

    }

It looks like the reset was performed because all values are on init state except the softreset bit stays 1.

On Page 1430 of Reference Manual Rev. 1, 04/2013 I found the following text

"When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped

registers. The following registers are reset: MCR (except the MDIS bit)

...

The SOFT_RST bit remains asserted while reset is pending, and is

automatically negated when reset completes.

.....

Soft reset cannot be applied while clocks are shut down in any of the low power modes. The module

should be first removed from low power mode, and then soft reset can be applied."

So the bit should switch to 0 when the reset finished, but not if no clock is assigned.

Is there a way to check if a clock is assigned and running and I am not in any powerdown mode.

Thank you

Wolfgang

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1,427 次查看
alejandrolozan1
NXP Employee
NXP Employee

Hi,

Which device are you using?

/Alejandro

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wolnet
Contributor III

Sorry,

I use an imx6 dual lite and I try to use this driver on FLEXCAN 1 and FLEXCAN 2

here my devicetree

#include "imx6dl.dtsi"

/*

* PAD settings

*/

&iomuxc {

flexcan1 {
   pinctrl_flexcan1_sigmatek: flexcan1grp-sigmatek {
   fsl,pins = <
   MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX NO_PAD_CTRL
   MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX NO_PAD_CTRL
   >;
   };

    };

    flexcan2 {

   pinctrl_flexcan2_sigmatek: flexcan2grp-sigmatek {
   fsl,pins = <
   MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX NO_PAD_CTRL
   MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX NO_PAD_CTRL
   >;
   };

    };

};

/*

* CAN

*/

&flexcan1 {

    pinctrl-names = "default";

    pinctrl-0 = <&pinctrl_flexcan1_sigmatek>;

    status = "okay";

};

&flexcan2 {

    pinctrl-names = "default";

    pinctrl-0 = <&pinctrl_flexcan2_sigmatek>;

    status = "okay";

};

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Yuri
NXP Employee
NXP Employee

Hello,

  The following may help :

https://community.nxp.com/message/345722 

Regards,

Yuri.

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