Fixing 'base address switching Change Err' which occurs randomly

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Fixing 'base address switching Change Err' which occurs randomly

8,494件の閲覧回数
kaartic_sn
Contributor III

Hi,

We are trying to add support for a new MIPI camera in the NXP i.MX 8M. It is a YUV camera. We are using the L4.14.78_1.0.0_MX8MQ BSP. We are getting 'base address switching Change Err' randomly when trying to stream. We made sure that the sensor side configuration was correct by evaluating the settings and clocks on a different platform. The we tried changing the MIPI receiver clock in the platform side i.e., the 'assigned-clock-rates' property in the following device tree entry. The device tree file is 'fsl-imx8mq.dtsi'.

    mipi_csi_1: mipi_csi1@30a70000 {
        compatible = "fsl,mxc-mipi-csi2_yav";
        reg = <0x0 0x30a70000 0x0 0x1000>; /* MIPI CSI1 Controller base addr */
        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk IMX8MQ_CLK_DUMMY>,
                <&clk IMX8MQ_CLK_CSI1_CORE>,
                <&clk IMX8MQ_CLK_CSI1_ESC>,
                <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
        clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
        assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
                  <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
                  <&clk IMX8MQ_CLK_CSI1_ESC>;
        assigned-clock-rates = <133000000>, <100000000>, <66000000>;
        power-domains = <&mipi_csi1_pd>;
        csis-phy-reset = <&src 0x4c 7>;
        phy-gpr = <&gpr 0x88>;
        status = "disabled";
    };

When changing the values to the following:

        assigned-clock-rates = <266000000>, <400000000>, <66000000>;

We are successfully able to stream all the resolutions at the expected frame rates. However, the camera doesn't work at random times and we get the 'base address switching Change Err' when it doesn't work. The only way to fix this issue is to reboot the board (once or sometimes multiple times). Then it would work normally and we get uninterrupted streaming as usual. This indicated that the values we've configured for the platform side clock might be the problem. We tried to fix this issue which occurs at random times by reducing the platform side clock and correspondingly the sensor's MIPI clock too. We decreased platform side clocks to the following value:

        assigned-clock-rates = <266000000>, <150000000>, <66000000>;

Now we are able to avoid the 'base address switching Change Err' issue that occurs at random times but couldn't achieve the expected frame rates as we have also reduced the sensor side MIPI clocks. It would we nice if someone could shed some light on how to correctly program the platform side clocks which seems to be the key to adding support for our camera? We believe that the sensor side configuration and clocks are correct as we have tested it in a different platform.


To summarize,

1. In what scenarios does one face the 'base address switching Change Err'?

2. How to correctly program the values for the 'assigned-clock-rates' property in the device tree for any MIPI CSI2 sensor?

3. Are we missing something here?

4. For previous generation processors i.e, i.MX6, there's a document which describes in detail on how to configure the host for different sensors. It would be great if such a document was made available for i.MX 8M as well.

Thanks,

Sivaraam

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711件の閲覧回数
weideding
Contributor II

I am using YUV422 8 bit (Data Type = 0x1E), No error when use 4 lanes, but the image is wrong mix. I think there is something wrong from MIPI-CSI to CSI brigde.

[ 40.438747] MIPI CSI2 HC register dump, mipi csi0
[ 40.443522] MIPI CSI2 HC num of lanes 0x100 = 0x3
[ 40.448748] MIPI CSI2 HC dis lanes 0x104 = 0x0
[ 40.454040] MIPI CSI2 HC BIT ERR 0x108 = 0x0
[ 40.459265] MIPI CSI2 HC IRQ STATUS 0x10C = 0x3f
[ 40.464639] MIPI CSI2 HC IRQ MASK 0x110 = 0x1ff
[ 40.470098] MIPI CSI2 HC ULPS STATUS 0x114 = 0x0
[ 40.475328] MIPI CSI2 HC DPHY ErrSotHS 0x118 = 0x0
[ 40.480550] MIPI CSI2 HC DPHY ErrSotSync 0x11c = 0x0
[ 40.485783] MIPI CSI2 HC DPHY ErrEsc 0x120 = 0x0
[ 40.490952] MIPI CSI2 HC DPHY ErrSyncEsc 0x124 = 0x0
[ 40.496181] MIPI CSI2 HC DPHY ErrControl 0x128 = 0x0
[ 40.501402] MIPI CSI2 HC DISABLE_PAYLOAD 0x12C = 0x0
[ 40.506635] MIPI CSI2 HC DISABLE_PAYLOAD 0x130 = 0x0
[ 40.511804] MIPI CSI2 HC IGNORE_VC 0x180 = 0x1
[ 40.517034] MIPI CSI2 HC VID_VC 0x184 = 0x1
[ 40.522206] MIPI CSI2 HC FIFO_SEND_LEVEL 0x188 = 0x40
[ 40.527523] MIPI CSI2 HC VID_VSYNC 0x18C = 0x0
[ 40.532747] MIPI CSI2 HC VID_SYNC_FP 0x190 = 0x0
[ 40.537980] MIPI CSI2 HC VID_HSYNC 0x194 = 0x0
[ 40.543149] MIPI CSI2 HC VID_HSYNC_BP 0x198 = 0x0

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711件の閲覧回数
weideding
Contributor II

4lanes can work now, reference manual says max is 125Mhz, it is wrong.  change it to 250Mhz,then ok.

pastedImage_1.png

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711件の閲覧回数
haidong_zheng
NXP Employee
NXP Employee

Hi Ding:

Don't touch those register, as 8MQ only support 1 channel. 

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711件の閲覧回数
igorpadykov
NXP Employee
NXP Employee

Hi Sivaraam

regarding 'base address switching Change Err' latest rev.1 4/2019 Reference Manual

gives description in sect.13.7.3.1 Data Transfer with the Embedded DMA Controllers

which provides more understanding for that error. More complete description gives

sect.20.5.15 Base Address Change Error Interrupt (BASEADDR_CHANGE_ERROR)

i.MX6SX Reference Manual
http://www.nxp.com/docs/en/reference-manual/IMX6SXRM.pdf

 To transfer data from the RxFIFO to the external memory, user should set the start
address in the frame buffer where the transferred data is stored, the parameters of the
frame buffers, and the parameters of the image coming from the sensor. The user can
have two frame buffers in the external memory. Each one will store a frame of image
coming from the sensor. The embedded DMA controller will first write the frame buffer1
and then frame buffer2. These two frame buffers will be written by turns. The start
address should be aligned in word and set in the CSIDMASA-FB1 and CSIDMASA-FB2
registers.

Regarding other questions, unfortunately so far there is no additional documentation

for porting new sensor and tweaking clocks, for new camera customizations may be

recommended to proceed with help of NXP Professional Services | NXP 

Best regards
igor
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