[FEC][DMA]how the dma find the correct address for the new packet and refresh the buffer address

[xuhaiwong7]

There is a question about the DMA process the packet for the FEC
(1) dmam alloc a buffer(fec_enet_init):
dma_addr_t bd_dma;
cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, GFP_KERNEL);
so the bd_dma is a Physical Address，cbd_base is a virt address
(2) the assign the bd_dma(Physical Address) to r&t descriptor : 
#define FEC_R_DES_START_1 0x160 /* Receive descriptor ring 1 */
#define FEC_X_DES_START_1 0x164 /* Transmit descriptor ring 1 */
#define FEC_R_DES_START_2 0x16c /* Receive descriptor ring 2 */
#define FEC_X_DES_START_2 0x170 /* Transmit descriptor ring 2 */
#define FEC_R_DES_START_0 0x180 /* Receive descriptor ring */
#define FEC_X_DES_START_0 0x184 /* Transmit descriptor ring */
#define FEC_R_DES_START(X) (((X) == 1) ? FEC_R_DES_START_1 : \
(((X) == 2) ? \
FEC_R_DES_START_2 : FEC_R_DES_START_0))
#define FEC_X_DES_START(X) (((X) == 1) ? FEC_X_DES_START_1 : \
(((X) == 2) ? \
FEC_X_DES_START_2 : FEC_X_DES_START_0))

writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));

(3)the virt address to bd.base/cur/last
rxq->bd.base = cbd_base;
rxq->bd.cur = cbd_base;
txq->bd.base = cbd_base;
txq->bd.cur = cbd_base;

(4)but I find the value of  r&t descriptor reg is not changed with the packet in or out :
(5)so how the dma find the correct address to used for the new packet and refresh the buffer address?
the below is my some print log:
 [ 1.792263] [fec]fep->hwp = ffff00000e6e0000
[ 1.796934] fec 5b040000.ethernet: 5b040000.ethernet supply phy not found, using dummy regulator
[ 1.805808] fec 5b040000.ethernet: Linked as a consumer to regulator.0
[ 1.812423] [fec]irq_cnt = 3
[ 1.815780] pps pps0: new PPS source ptp0
[ 1.819821] fep->total_tx_ring_size = 0x200
[ 1.824107] TX_RING_SIZE = 512
[ 1.828662] fep->total_tx_ring_size = 0x400
[ 1.832982] TX_RING_SIZE = 512
[ 1.837031] fep->total_tx_ring_size = 0x600
[ 1.841342] TX_RING_SIZE = 512
[ 1.845409] fep->rx_queue[0] = ffff80083b52c000
[ 1.850050] RX_RING_SIZE = 512
[ 1.853212] fep->total_rx_ring_size = 0x200
[ 1.857503] fep->rx_queue[1] = ffff80083b52e000
[ 1.862136] RX_RING_SIZE = 512
[ 1.865289] fep->total_rx_ring_size = 0x400
[ 1.869591] fep->rx_queue[2] = ffff80083b3c0000
[ 1.874220] RX_RING_SIZE = 512
[ 1.877370] fep->total_rx_ring_size = 0x600
[ 1.882619] cbd_base = ffff00000e730000, bd_dma = 0x96080000, bd_size = 98304
[ 1.889913] [fec]i=0, rxq->bd.reg_desc_active = ffff00000e6e0010, size=16384
[ 1.897071] [fec]i=0, rxq->bd.base = ffff00000e730000, rxq->bd.base->cbd_bufaddr = 0x0
[ 1.905087] [fec]i=0, rxq->bd.cur = ffff00000e730000, rxq->bd.cur->cbd_bufaddr = 0x0
[ 1.912931] [fec]i=0, rxq->bd.dma = 0x96080000.
[ 1.917562] [fec]i=1, rxq->bd.reg_desc_active = ffff00000e6e01e0, size=16384
[ 1.924712] [fec]i=1, rxq->bd.base = ffff00000e734000, rxq->bd.base->cbd_bufaddr = 0x0
[ 1.932734] [fec]i=1, rxq->bd.cur = ffff00000e734000, rxq->bd.cur->cbd_bufaddr = 0x0
[ 1.940637] [fec]i=1, rxq->bd.dma = 0x96084000.
[ 1.945270] [fec]i=2, rxq->bd.reg_desc_active = ffff00000e6e01e8, size=16384
[ 1.952414] [fec]i=2, rxq->bd.base = ffff00000e738000, rxq->bd.base->cbd_bufaddr = 0x0
[ 1.960435] [fec]i=2, rxq->bd.cur = ffff00000e738000, rxq->bd.cur->cbd_bufaddr = 0x0
[ 1.968276] [fec]i=2, rxq->bd.dma = 0x96088000.
[ 1.972909] [fec]i=0, txq->bd.reg_desc_active = ffff00000e6e0014
[ 1.979017] [fec]i=1, txq->bd.reg_desc_active = ffff00000e6e01e4
[ 1.985122] [fec]i=2, txq->bd.reg_desc_active = ffff00000e6e01ec
[ 1.991233] [fec]---- fec_restart ---- begin
[ 1.995608] [fec][bd init]q = 0,
[ 1.999033] [fec][bd init]q = 1,
[ 2.002454] [fec][bd init]q = 2,
[ 2.006072] [fec][rx desc]skip write 0x96080000 to ffff00000e6e0180
[ 2.012351] [fec][rx desc]skip write 0x96084000 to ffff00000e6e0160
[ 2.018631] [fec][rx desc]skip write 0x96088000 to ffff00000e6e016c
[ 2.024913] [fec][tx desc]skip write 0x9608c000 to ffff00000e6e0184
[ 2.031191] [fec][tx desc]skip write 0x96090000 to ffff00000e6e0164
[ 2.037473] [fec][tx desc]skip write 0x96094000 to ffff00000e6e0170
[ 2.043886] [fec]pdev->name = 5b040000.ethernet, irq_name = int0, irq = 120
[ 2.050902] [fec]pdev->name = 5b040000.ethernet, irq_name = int1, irq = 121
[ 2.057941] [fec]pdev->name = 5b040000.ethernet, irq_name = int2, irq = 122

<----fec_enet_new_rxbdp print
[ 4.444858] bdp = ffff00000e730000, skb =ffff80083aa31100: skb->data = ffff80083bf976c0 <--> bdp->cbd_bufaddr = 0xfc46b000
[ 4.457465] bdp = ffff00000e730020, skb =ffff80083aa31200: skb->data = ffff80083bf96d40 <--> bdp->cbd_bufaddr = 0xfc46b800
[ 4.471177] bdp = ffff00000e730040, skb =ffff80083aa31300: skb->data = ffff80083bf963c0 <--> bdp->cbd_bufaddr = 0xfc46c000

[Zhiming_Liu]

Hi @xuhaiwong7 

but I find the value of  r&t descriptor reg is not changed with the packet in or out :

-->Can you point which log about this r&t reg value?

From the log you provide, the value has changed in rxq structures