Hello,
I'm creating kernel driver for my client purposes, integrating VPU G1 capabilities of IMX8M Mini. No matter what I try, when I write 0x1 to SWREG1, starting decoding, I get "0x2101" from this register, which translates to:
- Decoder enabled
- Decoder IRQ
- Interrupt status bit bus. Error response from bus.
First two are OK, but the third one is a blocker. I passed DMA address received from
vb2_dma_contig_plane_dma_addr()
Hello,
The maximum size of the encoded frame depends on the input picture. If the encoder reaches the end of the output buffer, it will discard the current frame and return
VCENC_OUTPUT_BUFFER_OVERFLOW. Even if the current frame is lost, the encoding process can continue with a new frame which will be INTRA coded to assure that any errors are not propagated. You have to alignment in order to pass this buffer.
Regards
Hello,
I'm sorry, but I have trouble understanding. I am working on a decoder, using direct access to VPU registers, not VPU API, so I can't get an error like VCENC_OUTPUT_BUFFER_OVERFLOW. All I'm getting is bus error in SWREG1 register.