DDR3 Address Mirror Issues on MX6DL

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DDR3 Address Mirror Issues on MX6DL

Contributor III

Hi all,

     MX6DL supports DDR3 address mirror,I have read lot of documents,but I have some problems about this feature:

     1.This feature only can be applied to the second Rank. why?

     2. And our board has one Rank, I have enabled this feature, I didn't find some bugs,Could I open this feature?

     3. For this feature, the addr lines: A3,A4; A5,A6; A7,A8; BA0,BA1; they connect to each other, Why doesn't the W/R operation make any error? Actually,I can't understand  why do these pin can connect to each other?

   Please help me,thank you ~     

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NXP Employee
NXP Employee

Please refer to UDIMM JEDEC Standard for detailed description of mirror feature (requires registration)


Section 3.1 Address Mirroring Feature


There is a via grid located under the SDRAMs for wiring the CA signals (address, bank address, command, and control lines) to the SDRAM pins. The length of the traces from the vias to the SDRAMs places limitations on the bandwidth of the module. The shorter these traces, the higher the bandwidth. To extend the bandwidth of the CA bus for DDR3 modules, a scheme was defined to reduce the length of these traces.

The pins on the SDRAM are defined in a manner that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical support pins, do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are address pins A3, A4, A5, A6, A7, A8 and bank address pins BA0 and BA1. Rank 0 SDRAM pins are wired straight, with no mismatch between the connector pin assignment and the SDRAM pin assignment. Some of the Rank 1 SDRAM pins are cross wired as defined in the table. Pins not listed in the table are wired straight.

Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limitations however. When writing to the internal registers with a "load mode" operation, the specific address is required. This requires the controller to know if the rank is mirrored or not. This requires a few rules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a requirement that the second rank be mirrored. There is a bit assignment in the SPD that indicates whether the module has been designed with the mirrored feature or not. See the DDR3 UDIMM SPD specification for these details. The controller must read the SPD and have the capability of de-mirroring the address when accessing the second rank.


Also, see Figure 1 — Wiring Differences for Mirrored and Non-Mirrored Addresses

Now the answers:

1. No need to mirror rank0 signals when using recommended JEDEC UDIMM layout.

2. No need to mirror rank0 signals if the only one rank is used.

3. Cross-wired pins have no secondary functions.

Have a great day,

Note: If this post answers your question, please click the Correct Answer button. Thank you!

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